Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

Abstract: An image-sensing display device and an image processing method are provided. The image-sensing display device includes a substrate, banks, and sensor units. The banks and the sensor units are located on the substrate. Each of the sensor units includes first to fourth light-emitting devices and a photo sensor. The first to fourth light-emitting devices are located around a corresponding bank. The first to third light-emitting devices include a red light-emitting device, a green light-emitting device, and a blue light-emitting device. The first and fourth light-emitting devices are light-emitting devices of a same color. The photo sensor is located on the corresponding bank. The photo sensor includes a first electrode, a second electrode, and a sensing layer located between the first electrode and the second electrode. The first electrode and the second electrode respectively extend from the sensing layer along a first direction and a second direction.

Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.

Abstract: An optical semiconductor component package includes a base, a frame, a lid, and a light absorbing member located on an inner surface of the lid. The base is plate-like and has a first surface including a mount area in which an optical semiconductor component is mountable. The frame is located on the first surface and surrounds the mount area. The lid is plate-like and is bonded to the frame and covers the mount area. The light absorbing member is located on a second surface of the lid facing the mount area, and has a plurality of recesses on its surface.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.

Abstract: A method for producing a stacked electrode of an embodiment includes preparing a multi-layered graphene film, applying a dispersion liquid of metal nanowires onto the multi-layered graphene film, and removing a solvent from the dispersion liquid to prepare a metal wiring on the multi-layered graphene film.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode.

Abstract: One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.

Abstract: A semiconductor device capable of retaining data for a long time is provided. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without an increase in the number of manufacturing steps.

Abstract: The present disclosure relates to a display panel including a display area that can be stretched by including a plurality of stretching units and a peripheral area positioned at an edge of the display area. Each of the stretching units includes: a plurality of islands separately disposed to include a plurality of pixels disposed therein; a plurality of bridges extended from the islands to connect adjacent islands or to connect the islands with the peripheral area; and a plurality of openings disposed adjacent to the bridges, between the bridges, and between the bridges and the islands, wherein areas of the islands are gradually increased toward the peripheral area.

Abstract: A method of manufacturing a light emitting device includes: mounting light emitting elements on a collective substrate; arranging a first protruding member surrounding the light emitting elements; arranging a second protruding member between the light emitting elements; forming a cover member covering an upper end of the second protruding member, a lateral surface of each of the light emitting elements in a region surrounded by the first protruding member; and singulating the light emitting devices by cutting the cover member, the second protruding member, and the collective substrate at a portion including the second protruding member. The second protruding member is harder than the cover member. An upper end of the second protruding member is located lower than that of the first protruding member but higher than the upper surface of each of the light emitting elements.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: A method (200) for fabricating thin-film optoelectronic devices (100), the method comprising: providing a substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding at least one alkali metal (235), and forming at least one cavity (236, 610, 612, 613) at the surface of the absorber layer wherein forming of said at least one cavity is by dissolving away from said surface of the absorber layer at least one crystal aggregate comprising at least one alkali crystal comprising at least one alkali metal. The method (200) is advantageous for more environmentally-friendly production of photovoltaic devices (100) on flexible substrates with high photovoltaic conversion efficiency and faster production rate.

Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

Abstract: A multi-chip stack can include a first semiconductor device disposed between a plurality of electrical connections and the second semiconductor device. The first semiconductor device can include a first through via and a first electrostatic discharge (ESD) protection circuit connected to a first one of the electrical connections. The first ESD Protection circuit can have a first ESD protection structure. The first through via provides an electrical connection through the first semiconductor device from a first surface to an opposite surface of the first semiconductor device and between the first one of the plurality of electrical connections and a first terminal of the first circuit. The first terminal of the first circuit can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure formed on the second semiconductor device.