Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

Abstract: A multi-chip stack can include a first semiconductor device disposed between a plurality of electrical connections and the second semiconductor device. The first semiconductor device can include a first through via and a first electrostatic discharge (ESD) protection circuit connected to a first one of the electrical connections. The first ESD Protection circuit can have a first ESD protection structure. The first through via provides an electrical connection through the first semiconductor device from a first surface to an opposite surface of the first semiconductor device and between the first one of the plurality of electrical connections and a first terminal of the first circuit. The first terminal of the first circuit can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure formed on the second semiconductor device.

Abstract: An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.

Abstract: A novel iridium complex which can be applied in an organic electroluminescent light emitting device, an organic electrochemical light emitting device, or the like, and which is thermally stable and has excellent sublimabilities. An iridium complex characterized by being represented by General Formula (1) (in General Formula (1), R1 to R11 and R13, R14, and R18 represent a hydrogen atom, an alkyl group with 1 to 30 carbon atoms, an aryl group with 6 to 30 carbon atoms, a halogen atom, or a cyano group; R12, R15 to R17 and R19 represent a hydrogen atom, an alkyl group with 1 to 30 carbon atoms, a halogen atom, or a cyano group; the alkyl group may be substituted with an aryl group, a halogen atom, or a cyano group; the aryl group may be substituted with an alkyl group, a halogen atom, or a cyano group; adjacent R12 to R19 may bind to each other to form a condensed ring; and m is an integer of 1 or 2, n is an integer of 1 or 2, and m+n is 3).

Abstract: Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

Abstract: A display device includes first, second, and third insulating layers sequentially disposed on a substrate, a scan line disposed on the first insulating layer, an auxiliary power source line disposed on the second insulating layer, a data line disposed on the third insulating layer, a power source line disposed on the third insulating layer, a pixel circuit unit that includes transistors connected to the scan line, the data line, and the power source line, a bridge pattern disposed on the third insulating layer, and a light emitting diode connected to the pixel circuit unit through the bridge pattern, wherein the bridge pattern and the auxiliary power source line overlap each other to form an additional capacitor with the third insulating layer interposed therebetween.

Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

Abstract: A semiconductor device includes a metal member (15), a first semiconductor chip (13), a second semiconductor chip (14), a first solder (24) and a second solder (25). A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer (13a) connected to the metal member through a first solder (24) at a surface facing the metal member. The second semiconductor chip has a second metal layer (14a) connected to the metal member through a second solder (25) at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.

Abstract: Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Abstract: A sensor module, such as an acceleration sensor module, includes a leaded socket assembly covered by a housing. The leaded socket assembly includes a dual gauge lead frame, a sensor die, and various passive devices. The sensor die and the passive devices are mounted on the lead frame, and then the lead frame, sensor die, and passive devices are over-molded to form the leaded socket assembly. Neither the sensor module nor the socket assembly includes a printed circuit board, so many conventional sensor module assembly steps are bypassed.

Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.

Abstract: A head mounted display device according to an exemplary embodiment includes: a case; a display panel that is disposed in the case and is capable of displaying an image; and an optical system between the display panel and a user, wherein the display panel includes a pixel layer that includes a plurality of pixels capable of emitting light and a light blocking layer on the pixel layer and having a plurality of light blocking openings, and the area of a first area where the light blocking layer and the pixel are overlapped with each other in a plane view is gradually increased toward an outer portion of the display panel from a center portion of the display panel.

Abstract: A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region.

Abstract: The application provides a double-sided plastic fan-out package structure having an antenna structure. It includes a redistribution layer (RDL); a semiconductor chip, invertedly mounted on a first surface of the redistribution layer with a front surface facing downward; a first plastic encapsulation material layer, located on the first surface of the redistribution layer, encapsulating the semiconductor chip; a second plastic encapsulation material layer, located on a second surface of the redistribution layer; an antenna structure, located on a surface of the second plastic packaging material layer distant from the redistribution layer; an electrical connection structure, located inside the second plastic encapsulation material layer, and electrically connected to the antenna structure on the lower side of the redistribution layer. This structure can shield an interference signal of the antenna structure, thereby preventing the antenna structure from interfering the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface. The metal member is provided in the through-hole, and includes a cavity therein defined by an internal surface. The metal oxide film coats the internal surface.

Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Abstract: A lead frame used to produce a chip package includes a first lead frame section and a second lead frame section connected to one another by a bar, wherein the bar includes a first longitudinal section, a second longitudinal section and a third longitudinal section, the first longitudinal section adjoins the first lead frame section and the third longitudinal section adjoins the second lead frame section, the first longitudinal section and the third longitudinal section are oriented parallel to one another, the first longitudinal section and the second longitudinal section form an angle not equal to 180° and not equal to 90°, and the lead frame is planar.

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.