Abstract: A display device includes a substrate, a circuit layer on the substrate, a display layer on the circuit layer, at least one hole in a display area of the substrate that penetrates the substrate, the circuit layer, and the display layer, and at least two grooves that surround the at least one hole, where each of the at least two grooves has an undercut structure. The substrate includes a first substrate, a first inorganic layer, a second substrate, and a second inorganic layer, which are sequentially stacked, and each of the at least two grooves extends down from the display layer into the second substrate.

Abstract: The present disclosure provides a light emitting device and a method for manufacturing the same, and a display device, and relates to the field of display technology. The light emitting device includes: a light emitting unit; an encapsulating layer located on one side of the light emitting unit, wherein the encapsulating layer includes a reflective layer; an adhesive layer located on one side of the encapsulating layer away from the light emitting unit, wherein the adhesive layer includes an adhesive material; and a color filter layer located on one side of the adhesive layer away from the encapsulating layer, wherein the reflective layer is configured to reflect a light that cures the adhesive material.

Abstract: A light emitting element includes a semiconductor structure including a first layer including a first and a second regions, and a second layer above the second region, the first region including extending portions each extending into the second region from an outer peripheral region; a first insulating layer including first through-holes respectively located on the extending portions, and a second through-hole located above the second region; a second insulating layer including a third and a fourth through-holes; a first external electrode connected with the first layer via the first through-holes; and a second external electrode connected with the second layer via the second through-hole. The extending portions are each located in an area, on a top surface of the first layer, other than an area overlapping any of corner portions of the first external electrode and other than an area overlapping any of corner portions of the second external electrode.

Abstract: A display device according to an embodiment of the present invention includes: a substrate that includes a display region and a peripheral region; a display element that is provided on the display region of the substrate; and an electronic component that is provided in the peripheral region on an opposite surface from a surface of the substrate on which the display element is provided, wherein the substrate includes one or more through holes in the peripheral region, the one or more through holes include a through electrode formed by a laminate structure of a plurality of conductive layers, and the through electrodes electrically connect the display element to the electronic component.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure.

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.

Abstract: A display device includes a substrate that includes a display region and a non-display region that surrounds the display region, a plurality of pixels disposed on the display region of the substrate, a plurality of dam members disposed on the non-display region of the substrate that surround the display region, a first encapsulation layer disposed on the substrate that covers the pixels and the dam members, and a second encapsulation layer disposed on the first encapsulation layer and in a region between the display region and a dam member of the plurality of the dam members that is adjacent to the display region. A surface roughness of a top surface of the second encapsulation layer is greater than a surface roughness of a top surface of the first encapsulation layer.

Abstract: A pixel structure, the pixel structure comprising a plurality of pixels arranged in an array, each pixel comprising three sub-pixels of different colours arranged in two adjacent rows; the plurality of pixels also comprise a plurality of first pixels and a plurality of second pixels, the plurality of first pixels and the plurality of second pixels being arranged alternately along the row direction; along the row direction, one sub-pixel of each first pixel is positioned in the same row as two sub-pixels of the adjacent second pixel, and the other two sub-pixels of each first pixel are positioned in the same row as the other sub-pixel in the adjacent second sub-pixel; and two sub-pixels positioned in different rows in each first pixel are respectively adjacent to the sub-pixels of the same corresponding colour in an adjacent second pixel.

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

Abstract: A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: A light emitting device package may include: a light emitting structure including a plurality of light emitting regions configured to emit light, respectively; a plurality of light adjusting layers formed above the light emitting regions to change characteristics of the light emitted from the light emitting regions, respectively; a plurality of electrodes configured to control the light emitting regions to emit the light, respectively; and an isolation insulating layer disposed between the light emitting regions to insulate the light emitting regions from one another, the isolation insulating layer forming a continuous structure with respect to the light emitting regions.

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

Abstract: Provided is a semiconductor device capable of having simple wiring in mounting the semiconductor device. The semiconductor device includes at least one P-terminal, at least one N-terminal, a power output terminal, at least one power supply terminal, at least one ground (GND) terminal, at least one control terminal, and a package that is rectangular in a plan view and accommodates an insulated gate bipolar transistor (IGBT) being a high-side switching element, an IGBT being a low-side switching element, and a control circuit. The at least one control terminal is disposed on a first side of the package, opposite to a second side on which the power output terminal is disposed. The at least one P-terminal, the at least one N-terminal, the at least one power supply terminal, and the at least one GND terminal are disposed on a third side of the package, orthogonal to the second side.

Abstract: Embodiments disclose a radiator component and a heat dissipation system for a power semiconductor device. The radiator component for a power semiconductor device includes a heat dissipation body including an inner-ring substrate, an outer-ring substrate, and a plurality of heat sinks. In an embodiment, the outer-ring substrate surrounds the inner-ring substrate and the plurality of heat sinks are arranged between the inner-ring substrate and the outer-ring substrate. One or more first power semiconductor device arrangement positions are provided on an inner circumferential surface of the inner-ring substrate and one or more second power semiconductor device arrangement positions are arranged on an outer circumferential surface of the outer-ring substrate. The radiator component further includes a fan component. The embodiments can save on space, reduce costs, improve the heat dissipation efficiency, and avoid the problem of disturbances between a plurality of fans.

Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.