Patents Examined by José R. Diaz
  • Semiconductor device package and method of manufacturing the same
    Patent number: 10629519
    Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Pixel array substrate
    Patent number: 10629634
    Abstract: A pixel array substrate includes signal lines arranged in an arranging direction, pixel structures electrically connected to the signal lines, a driving element and fan-out traces. Each of the fan-out traces is electrically connected to one of the signal lines and the driving element. A fan-out trace group includes a first fan-out trace and a second fan-out trace. A main portion of the first fan-out trace extends in a first direction, and the first direction and the arranging direction have a first angle ? therebetween. A main portion of the second fan-out trace extends in a second direction, and the second direction and the arranging direction have a second angle ? therebetween. The first angle ? is different from the second angle ?. In addition, another pixel array substrate has also been proposed.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: April 21, 2020
    Assignee: Au Optronics Corporation
    Inventor: Bo-Xuan Liao
  • Light emitting device package
    Patent number: 10629782
    Abstract: A light emitting device package may include: a light emitting structure including a plurality of light emitting regions configured to emit light, respectively; a plurality of light adjusting layers formed above the light emitting regions to change characteristics of the light emitted from the light emitting regions, respectively; a plurality of electrodes configured to control the light emitting regions to emit the light, respectively; and an isolation insulating layer disposed between the light emitting regions to insulate the light emitting regions from one another, the isolation insulating layer forming a continuous structure with respect to the light emitting regions.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Il Kim, Hyong Sik Won, Wan Tae Lim, Nam Goo Cha
  • Thin film transistor array panel
    Patent number: 10629624
    Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 21, 2020
    Assignees: SAMSUNG DISPLAY CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae Heung Ha, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho, Young Cheol Joo, Hyeong Joon Kim, Eun-Kil Park, Sang Jin Han
  • Semiconductor device
    Patent number: 10622280
    Abstract: A semiconductor device includes a semiconductor element, a cooler, and a heat conductive body. The cooler faces one surface of the semiconductor element, and has a flow passage of a coolant. As viewed from the flow direction of the coolant, a width of the flow passage is wider than a width of the semiconductor element. The heat conductive body is made from graphite having such an anisotropy that a heat conductivity in the in-plane direction of a predetermined surface is higher than a heat conductivity in the normal direction of the predetermined surface. The width of the heat conductive body is wider than the width of the semiconductor element as viewed from the flow direction of the coolant. The heat conductive body is configured such that the predetermined surface is non-parallel to both of the flow direction of the coolant and the one surface of the semiconductor element.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 14, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masataka Deguchi
  • FinFET including tunable fin height and tunable fin width ratio
    Patent number: 10622357
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • MEMS isolation platform with three-dimensional vibration and stress isolation
    Patent number: 10611628
    Abstract: A microelectromechanical vibration and stress isolation system is provided. The system includes an isolation platform configured to support a transducer and having an outer perimeter. A frame surrounds the isolation platform and has inner edge surfaces that are spaced from and face the outer edge surfaces of the platform. A spring connects the isolation platform to the frame. The spring is generally L-shaped, having a first leg that connects one inner edge surface to an outer edge surface while extending around a corner of the platform.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 7, 2020
    Assignee: EPACK, INC.
    Inventors: Sangwoo Lee, Jay Mitchell, Onnop Srivannavit
  • Display panel
    Patent number: 10613400
    Abstract: A display panel including a first substrate, a second substrate and a display medium is provided. The first substrate includes a base substrate, a gate, an active layer, a source, a drain, and a shielding structure. The gate is disposed on the base substrate. The active layer is electrically insulated from and disposed correspondingly to the gate. The source and the drain are electrically connected to the active layer. The shielding structure is disposed on the active layer and overlaps with at least part of the active layer. The shielding structure includes a metal layer and a metal oxide or metal nitride layer. The shielding structure is electrically insulated from the source. The display medium is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 7, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hsiao-Ping Lai, Chao-Liang Lu, Tzu-Min Yan, Tsau-Hua Hsieh
  • Semiconductor memory device and method of manufacturing semiconductor memory device
    Patent number: 10608098
    Abstract: A semiconductor memory device according to an embodiment includes a slit-side end portion of an insulating layer includes a main body of the insulating layer, a first thin layer thinner than the main body and extending from an end portion closer to an upper surface of the main body, the end portion facing the slit, toward the slit, and a second thin layer thinner than the main body and extending from an end portion closer to a lower surface of the main body, the end portion facing the slit, toward the slit, and the insulating layer includes an air gap layer surrounded by the main body, the first thin layer, and the second thin layer in the slit-side end portion.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kiyomitsu Yoshida
  • Method for producing a conductive through-plating for a substrate as well as conductive through-plating
    Patent number: 10607888
    Abstract: A conductive through-plating for a substrate includes a metal component, a first conductive structure situated on or in the environment of a surface of the substrate, and a second conductive structure situated on or in the environment of a further surface of the substrate. A method for producing the through-plating includes, in a first step, at least partially applying above the surface a grid structure that includes a group of openings; in a second step following the first step, carrying out an etching producing a trench in the substrate and at least partially also underneath the group of openings; and, in a fifth step following the second step, carrying out a metallization situating a metal component at least partially in the trench such that the metal component is part of a seal sealing the trench in the area of the surface.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Christoph Schelling, Johannes Classen, Simon Genter
  • Semiconductor device
    Patent number: 10607964
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Yukifumi Oyama, Keisuke Taniguchi
  • Organic light emitting diode and organic light emitting display panel having the same
    Patent number: 10573840
    Abstract: An organic light emitting diode and an organic light emitting display panel, the organic light emitting diode including an anode disposed on a base layer; a first organic light emitting layer disposed on the anode; a cathode disposed on the first organic light emitting layer; and an electron control layer disposed between the first organic light emitting layer and the cathode, the electron control layer including ytterbium, wherein the cathode includes a first inorganic compound layer contacting the electron control layer to form a P-N junction with the electron control layer; and a conductive layer disposed on the first inorganic compound layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minwoo Lee, Youngmo Koo, Okkeun Song
  • Display device
    Patent number: 10566578
    Abstract: A display device includes a first substrate, a coloring layer formed on the first substrate, a transparent insulating layer having a first refractive index formed on the coloring layer, a first transparent electrode having a higher second refractive index than the first refractive index formed on the transparent insulating layer, an organic layer having a light emitting layer formed on the first transparent electrode, and a second transparent electrode formed on the organic layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 18, 2020
    Assignee: Japan Display Inc.
    Inventors: Shigeru Sakamoto, Hajime Akimoto
  • BEOL capacitor through airgap metallization
    Patent number: 10566414
    Abstract: A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher Waskiewicz
  • Semiconductor device and method of manufacturing the same
    Patent number: 10566347
    Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Methods and apparatus for an image sensor
    Patent number: 10559618
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for an image sensor. The image sensor may comprise a color filter with a convex surface and a corresponding underlying dielectric element. The convex surface of the color filter is parallel to a convex surface of the dielectric element, wherein the convex shape of the color filter is substantially equal to the convex shape of the dielectric element.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Swarnal Borthakur
  • Doping organic semiconductors
    Patent number: 10559753
    Abstract: We describe a method for reducing a parasitic resistance at an interface between a conducting electrode region and an organic semiconductor in a thin film transistor, the method comprising: providing a solution comprising a dopant for doping said semiconductor, and depositing said solution onto said semiconductor and/or said conducting electrode region to selectively dope said semiconductor adjacent said interface between said conducting electrode region and said semiconductor, wherein depositing said solution comprises inkjet-printing said solution.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: February 11, 2020
    Assignee: Cambridge Display Technology Limited
    Inventors: Jeremy Burroughes, Christopher Newsome, Daniel Tobjörk, Mark Dowling
  • Semiconductor device with contact pad and fabrication method therefore
    Patent number: 10553479
    Abstract: A method of fabricating a semiconductor structure includes forming a conductive structure over a first passivation layer, depositing a first dielectric film continuously over the conductive structure, depositing a second dielectric film continuously over the first dielectric film, and depositing a third dielectric film over the second dielectric film. A portion of the third dielectric film is in contact with a portion of the first dielectric film.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsu Yen, Chen-Hui Yang, Yu Chuan Hsu
  • Thin film transistor array substrate and organic light-emitting display device including the same
    Patent number: 10546906
    Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Won-Se Lee
  • Light-emitting device
    Patent number: 10546824
    Abstract: The present disclosure provides a light emitting device including an LED array including a plurality of LED cells connected in series disposed on a single substrate; wherein each LED cell includes a first edge, a second edge, a third edge, and a fourth edge, and wherein the LED array includes a first LED and a second LED, the first edge of the first LED is adjacent to the third edge of the second LED; a first trench, disposed between the first LED cell and the second LED; and a first conducting metal, disposed on the first trench, the first edge of the first LED and the third edge of the second LED, and electrically connecting the first LED and the second LED in series; wherein the first LED and/or the second LED includes a round corner in a top view.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: January 28, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao Hsing Chen, Chien Fu Shen, Tsun Kai Ko, Schang Jing Hon, Hsin Mao Liu