Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

Abstract: Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.

Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.

Abstract: A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.

Abstract: In a method for manufacturing a semiconductor structure, a substrate is provided; a stack layer is formed on the substrate, the stack layer including an interfacial layer, a high-k dielectric layer and a work function composite layer which are sequentially stacked; a transition layer is formed on the stack layer; and a metal gate layer is formed on the transition layer. The work function composite layer is prepared by a physical vapor deposition process.

Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

Abstract: Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalls of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Abstract: A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

Abstract: A method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process. The non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness.

Abstract: A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate.

Abstract: A semiconductor device, including: a substrate; a gate oxide layer located in or on the substrate; and a gate located on a surface of the gate oxide layer, the gate including a monocrystalline silicon layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

Abstract: A display panel includes a substrate; multiple first electrode signal lines formed on the substrate; and multiple isolation columns located on a side of the multiple first electrode signal lines facing away from the substrate. The display panel includes multiple pixel regions and multiple partition regions, each of the multiple pixel regions is internally provided with a respective one of the multiple isolation columns, each of the multiple isolation columns is internally provided with multiple pixel openings, and each of the multiple pixel openings is internally provided with a first electrode and a light-emitting function layer located on a side of the first electrode facing away from the substrate, the first electrode is electrically connected to a corresponding one of the multiple first electrode signal lines, and the multiple partition regions are used for partitioning a second electrode between two adjacent pixel regions.