Patents Examined by Joseph C Nicely
  • Patent number: 11232947
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Wei Chu, Ying-Chi Su, Yu-Kai Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11233158
    Abstract: A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 25, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Mingjiao Liu
  • Patent number: 11227212
    Abstract: Semiconductor devices and methods of forming the same include forming a drain/gate contact, in an opening of a layer of dielectric material, that includes a portion that extends up along sidewalls of the opening. A drain layer is formed on a bottom surface of the drain/gate contact. A trapped insulator layer is formed on sidewalls of the drain/gate contact. A channel layer is formed in the opening. A source layer is formed on the channel layer.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11217577
    Abstract: A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
  • Patent number: 11217528
    Abstract: A semiconductor structure includes: a buried power rail disposed between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure located in a first cell, the second fin structure located in a second cell abutting the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track disposed in a M1 layer extending in a second direction in the horizontal plane. At an intersection of the buried power rail and the M1 metal track, the semiconductor structure further includes an electrically conductive path to provide the first voltage to the M1 metal track, the electrically conductive path having a first metal zero (M0) metal track extending in the first direction over the boundary line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 11217533
    Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 4, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Steven Robert Soss, Steven John Bentley, Julien Frougier
  • Patent number: 11211428
    Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 28, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Patent number: 11211420
    Abstract: An image sensor includes a substrate including a plurality of pixel regions and having a trench between the pixel regions, a photoelectric conversion part in the substrate of each of the pixel regions, and a device isolation pattern in the trench. The device isolation pattern defines an air gap. The device isolation pattern has an intermediate portion and an upper portion narrower than the intermediate portion.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Ki Lee, Minwook Jung
  • Patent number: 11205694
    Abstract: An organic light-emitting display apparatus includes a lower substrate having a display area, and a sealing area outside of the display area, an upper substrate facing the lower substrate, a display unit at the display area, a sealing member at the sealing area, and adhering the upper substrate to the lower substrate, a metal pattern layer between the lower substrate and the sealing member, and defining a plurality of through-portions, a first metal layer along an edge of the display unit, and spaced from the metal pattern layer, and a plurality of metal patterns having island shapes between the metal pattern layer and the first metal layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joonyung Jang
  • Patent number: 11205630
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • Patent number: 11205655
    Abstract: A method for manufacturing a semiconductor device includes a step of reducing a thickness of a silicon oxide film embedded in an element isolation trench including fins in order to form protruded fins. In the step, the silicon oxide film is etched while covering part of an upper surface of the silicon oxide film with a resist pattern. At this time, the resist pattern is formed such that a distance between the fin and the resist pattern is equal to or less than a predetermined interval which is an arrangement interval of the plurality of fins.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Hayashi
  • Patent number: 11205723
    Abstract: Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ardasheir Rahman, Brent Anderson, Junli Wang, Stuart Sieg, Christopher J. Waskiewicz
  • Patent number: 11201240
    Abstract: A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer and having a first region and a second region; a first semiconductor region of second conductivity type provided on the first region; a second semiconductor region of first conductivity type provided on the first semiconductor region; a second electrode provided in a first trench reaching the first region from above the first semiconductor region, the second electrode facing the first semiconductor region via a first insulating film, the second electrode being electrically connected to a first electrode provided above the first semiconductor layer; a fourth electrode provided below the second electrode in the first trench, the fourth electrode facing the first region via a second insulating film, the fourth electrode being electrically connected to a third electrode provided on the second semiconductor region and electrically
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: December 14, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masatoshi Arai
  • Patent number: 11201153
    Abstract: Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek, Dechao Guo
  • Patent number: 11195874
    Abstract: An image sensor array formed on a flexible first substrate is supported by a flexible second substrate attached thereto. The second substrate has a top surface with an adhesive thereon for attaching the substrates together. The adhesive is on a portion of the second substrate directly beneath the image sensor array to allow selective formation of the second substrate.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 7, 2021
    Assignee: Carestream Health, Inc.
    Inventors: Timothy J. Wojcik, Ravi K. Mruthyunjaya, Bradley S. Jadrich
  • Patent number: 11195977
    Abstract: A light emitting device includes a light emitting element including a first surface; a light guide member covering at least a part of a lateral surface of the light emitting element; a first wavelength conversion member covering the first surface and including a first wavelength conversion particles; and a reflective member being in contact with the light emitting element. The first wavelength conversion member has a thickness of 60 ?m or more and 120 ?m or less. The first wavelength conversion particles have an average particle size of 4 ?m or longer and 12 ?m or smaller; the first wavelength conversion particles have a central particle size of 4 ?m or longer and 12 ?m or smaller. A weight ratio of the first wavelength conversion particles is 60% by weight or more and 75% by weight or less with respect to the total weight of the first wavelength conversion member.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 7, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Tetsuya Ishikawa
  • Patent number: 11195949
    Abstract: In a general aspect, a laterally diffused metal-oxide-semiconductor (LDMOS) transistor can include: a substrate of a first conductivity type; a buried well region of a second conductivity type disposed in the substrate; a body region of the first conductivity type disposed on the buried well region, a drift region of the second conductivity type disposed in the body region, a drain implant of the second conductivity type disposed in the drift region; a source implant of the second conductivity type disposed in the body region; and a gate structure disposed on the drift region. The gate structure can include: a field plate including a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor can also include a drain contact extending through the field plate and defining an Ohmic contact with the drain implant.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: December 7, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Cho Chiu Ma
  • Patent number: 11195947
    Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 7, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson, Srikanth Balaji Samavedam
  • Patent number: 11189763
    Abstract: A backlight structure is provided. The backlight structure includes a substrate, a light emitting diode array layer disposed on the substrate, a planarization layer disposed on the light emitting diode array layer, a composite medium layer disposed on the planarization layer, a metal gate line layer including a plurality of metal lines disposed on the composite medium layer, a fluorescent layer disposed on the metal gate line layer, and a diffusion layer disposed on the fluorescent layer, wherein the composite medium layer includes a first medium, a second medium, and a third medium, the second medium is interposed between the first medium and the third medium, and each of a refractive index of the first medium and a refractive index of the third medium is less than a refractive index of the second medium.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 30, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guowei Zha
  • Patent number: 11189615
    Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Soo Hong, Jeong Yun Lee, Geum Jung Seong, Jin Won Lee, Hyun Ho Jung