Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Abstract: The present invention provides a trench gate structure and a method of forming the same. The method comprises steps of forming a first trench on the surface of a substrate, a surface of a bottom of the first trench comprising a crystal face belonging to the first family of crystal faces, and a surface of a sidewall of the first trench comprising another crystal face belonging to a second family of crystal faces. With a face-selective wet etching, a specific crystal face is presented on the surface of the bottom of the trench and a thicker gate oxide layer is formed thereon after performing thermal oxidation to avoid from failure due to thinner gate oxide layer on the surface of the bottom, increase breakdown voltage, and improve reliability of the device.

Abstract: A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.

Abstract: A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.

Abstract: A display device includes: a substrate; a semiconductor layer; a gate electrode overlapping the semiconductor layer; a common voltage line disposed on a same layer as the gate electrode; a common voltage line anti-oxidation layer disposed on the common voltage line; an interlayer insulating layer; source and drain electrodes disposed on the interlayer insulating layer; and a common voltage applying electrode disposed on a same layer as the source electrode and the drain electrode. The common voltage applying electrode is connected to the common voltage line through a first contact hole formed in the interlayer insulating layer, the common voltage line anti-oxidation layer includes an opening overlapping the common voltage line, the interlayer insulating layer is disposed in the opening, a width of the opening is smaller than a width of the common voltage line, and the first contact hole is disposed in the opening in a plan view.

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

Abstract: A semiconductor device including a protected element, an element isolation region, a contact region, and a shield region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. A periphery of the diode is surrounded by the element isolation region. The contact region is arranged at a portion on a main face of the anode region, is set with a same conductivity type as the anode region, and is set with a higher impurity concentration than the anode region. The shield region is arranged between the cathode region and the contact region so as to extend from the main face of the anode region as far as a region deeper than a depth of the contact region and shallower than the anode region. The shield region is configured including a semiconductor region with an opposite conductivity type to the anode region.

Abstract: A method for manufacturing a semiconductor device includes steps of forming a protective film on a semiconductor substrate, forming a resist film on the protective film such that the resist film includes a region where the resist film becomes thicker from a drain electrode to a source electrode, forming a first opening in the resist film by irradiating the resist film in the region with an electron beam and developing the resist film, forming a second opening that exposes an upper surface of the semiconductor substrate by removing the protective film using the resist film in which the first opening is formed as a mask, forming a third opening in the resist film by further developing the resist film after forming the second opening, the third opening being formed by expanding the first opening toward the drain electrode, and forming a gate electrode in the second and the third openings.

Abstract: Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.

Abstract: A semiconductor device includes a region of semiconductor material and a trench gate structure. The trench gate structure includes an active trench, a shield dielectric layer in a lower portion of the active trench, and a shield electrode of a first polycrystalline semiconductor material adjacent to the shield dielectric layer. A gate dielectric layer is adjacent to an upper portion of the active trench and a gate electrode of a second polycrystalline semiconductor material is adjacent to the gate dielectric layer. A shield conductive layer of a first conductive material is adjacent to the shield electrode and a gate conductive layer of the first conductive material is adjacent to the gate electrode. A dielectric fill structure is in the active trench electrically isolating the gate electrode and the gate conductive layer from the shield electrode and the shield conductive layer. In some examples, the semiconductor device includes a trench shield contact structure that includes the shield conductive layer.

Abstract: RMG techniques for VFET formation using a chamfering process are provided. In one aspect, a method of forming a VFET device includes: patterning fins adjacent to one another in a substrate; forming bottom source/drains at a base of the fins; forming bottom spacers over the bottom source/drains; forming sacrificial gates alongside the fins; forming top source/drains at a top of the fins; forming top spacers surrounding the top source/drains; removing the sacrificial gates; depositing a high-? gate dielectric along sidewalls of the fins; removing the high-? gate dielectric from an opening between adjacent top spacers; depositing at least a first workfunction-setting metal layer onto the high-? gate dielectric; removing the first workfunction-setting metal layer from the opening between the adjacent top spacers; and depositing at least a second workfunction-setting metal layer onto the first workfunction-setting metal layer to form replacement metal gates. A VFET device is also provided.

Abstract: Disclosed are an array substrate and a display device. In some embodiments of the disclosure, at least one multi-access selector arranged proximate to a first non-right-angled edge is segmented into a plurality of sub-units, and orthographic projections of at least two of the sub-units are stagger in a Y direction, the Y direction is perpendicular to a X direction in which gate lines extend.

Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

Abstract: A method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process. The non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

Abstract: A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

Abstract: A semiconductor device is provided, including: a semiconductor substrate having a first conductivity type of drift region; a transistor section having a gate trench section on an upper surface of the semiconductor substrate; a diode section having a first conductivity type of cathode region on a lower surface of the semiconductor substrate, the cathode region having a higher doping concentration than the drift region; and a buffering region arranged between the transistor section and the diode section, the diode section having a first upper surface side lifetime control region where a first valley portion is provided in a carrier lifetime distribution in a depth direction of the semiconductor substrate, and the buffering region having a second upper surface side lifetime control region where a second valley portion is provided in the carrier lifetime distribution, the second valley portion being wider, in the depth direction, than the first valley portion.