Abstract: Aspects capture test coverage in a distributed system, wherein a processor instigates execution of a unique hypertext transfer request protocol test case within a distributed system of different, networked servers. The header of the unique test case includes a unique name for the unique test case, and the distributed system servers are each configured to, in response to processing a test case, generate a time-stamped log entry that includes header data for the processed test case and a uniform resource locator address of the processing server. The processor thus maps the unique test case to a subset of the distributed system servers as endpoint servers of the unique test case, in response to determining that the uniform resource locator addresses of each of the subset endpoint servers are listed within generated log entries of the endpoint servers in association with the unique test case name.

Abstract: A processor may identify, using historical data, an amount of computing resources consumed to remedy the failure with an automatic remedy step. The processor may determine that the amount of consumed computing resources to remedy the failure is less than an amount of computing resources consumed by restarting the process. The processor may perform the automatic remedy step. The processor may identify that the automatic remedy step has failed. The processor may determine a waiting period based on an estimated time to receive a user response to the failure and an estimated load on the computing cluster. The processor may display a generated alert to a user during the waiting period. The processor may identify that no user input has been received during the waiting period. The processor may release computing resources corresponding to the process.

Abstract: Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

Abstract: Disclosed are hardware and techniques for correcting computer process faults by identifying risk associated with correcting a computer process fault and computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a stream of process break flags from a monitoring component coupled to the network. Each computer process break flag in the stream of computer process break flags indicates a process fault detected by the monitoring component and is correlated to a corrective response. The break flag and the corrective response are assigned a risk. A risk matrix accounts for interdependencies between computer processes and identified corrective actions. A final response strategy that corrects the computer process faults is determined using the assigned risk and computer system interdependence.

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

Abstract: A system and a method for predicting errors and failure of an application and performing preventive maintenance measures is disclosed. The present invention provides for generating timestamped event logs and extracting data which includes application Id, service Id, user Id, host, error information, resource information, user request data and frequently used execution sequences of associated software components. Further, multiple user requests are modelled based on information extracted from the timestamped event logs and an execution sequence of associated software components is created based on data extracted from timestamped event logs. Further, an execution scheme is generated based on modelled user requests, execution sequence of associated applications and resource status.

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.

Abstract: A computing device can monitor a set of memory usage metrics of the computing device. Based on historical memory usage data and the set of memory usage metrics, the computing device can determine whether memory usage will exceed a critical memory threshold at a future instance in time. In response to determining that the memory usage will exceed the critical memory threshold at the future instance in time, the computing device can degrade one or more application features of an application executing on the computing device.

Abstract: Rehabilitating storage devices in a storage array that includes a plurality of storage devices, including: receiving a request to rehabilitate a storage device that is operating outside of a defined range of expected operating parameters; selecting, from a hierarchy of rehabilitative actions that can be performed on the storage device, a rehabilitative action to perform on a storage device in dependence upon information describing a number of times that one or more of the rehabilitative actions have been performed on the storage device; and initiating execution of the selected rehabilitative action.

Abstract: A system and method for automatic and dynamic virtual machine (VM) group membership adjustment to identify and maintain VM groupings for maintaining a data consistency and availability at a computer recovery site in response to a disaster event. Based on a hybrid approach of network and storage analytics using cognitive methods, the system automatically groups the VMs based on patterns of data exchanged between the VMs. The system can store the patterns found during the analysis, find the critical elements in those patterns (like VMs playing the key role of DB server), match the patterns and use them in case a detected failure to make the system functional again at the recovery site. The system stores the communications traffic patterns learned during the network analysis and uses analytics to form or change the VM grouping, and can perform the pattern matching to quickly readjust the group.

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.

Abstract: Methods and systems for detecting anomalous behavior include performing a principal component analysis on a plurality of key performance indicators (KPIs) to determine a set of principal axes. The KPIs are clustered in a space defined by the set of principal axes. Local anomalies are determined in the clustered KPIs by comparing, for each individual KPI in clusters that conform to a Gaussian distribution, a distance from a respective cluster mean to a threshold. Structural anomalies are determined in the clustered KPIs. The structural and local anomalies are classified based on historical information. A management action is performed based on the classified structural and local anomalies.

Abstract: Methods and systems for detecting anomalous behavior include performing a principal component analysis on a plurality of key performance indicators (KPIs) to determine a set of principal axes. The KPIs are clustered in a space defined by the set of principal axes. Local and structural anomalies are determined in the clustered KPIs. The structural and local anomalies are classified based on historical information. A transformation is performed from a space based on the principal axes to an original space. It is determined whether each of the local and structural anomalies is a global or a local anomaly. A management action is performed based on the classified structural and local anomalies.

Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.

Abstract: A system and method for connected vehicle sequence anomaly detection. The method includes creating a normal sequence profile for a group of connected vehicles based on a plurality of first messages by training a normal behavior model using unsupervised machine learning with respect to potential sequences, the normal sequence profile defining normal sequences and triggers, wherein each of the plurality of normal sequences is associated with a timeframe, wherein each sequence is a series of condition combinations; preprocessing a second data set by generating a plurality of second messages in a unified format; identifying at least one instance of the plurality of triggers in the plurality of second messages; and detecting at least one abnormal sequence based on the identified at least one instance and the normal sequence profile, wherein an abnormal sequence is detected when none of the plurality of normal sequences is identified in the second data set.

Abstract: Embodiments of the present disclosure provide a method and a device for managing storage system. In an embodiment, a plurality of RAID stripes to be reconstructed in the storage system are determined. A first RAID stripe is selected from a plurality of RAID stripes based on a plurality of I/O load states at a disk extent level for the plurality of RAID stripes at a first storage processor in the storage system, the first RAID having a high I/O load at the disk extent level. Then, a first disk extent for reconstructing the first RAID stripe is determined and the first storage processor is configured to reconstruct data for the first RAID stripe at the first disk extent. A corresponding device to implement the method is further disclosed.

Abstract: A system for monitoring and maintaining aircraft cargos includes a plurality of master control panels each operatively connected with at least one Line Replaceable Unit (LRU) operating in a cargo compartment of an aircraft, and at least one unit load device (ULD). The at least one ULD and at least one LRU are configured to move a cargo unit in the cargo compartment based on a control signal from the master control panel. The system also includes a command unit operatively connected with each control panel of the plurality of master control panels. The command unit includes a processor configured to retrieve a status of the cargo from each of the plurality of master control panels, and display, on an output device, a status of the at least one ULD of a plurality of ULDs and a status of the at least one LRU via the processor.

Abstract: A controller includes an interface and storage circuitry. The interface communicates with one or more memory devices, each of the memory devices includes multiple memory cells organized in memory blocks. The storage circuitry is configured to perform multiple storage operations to the memory cells in the one or more memory devices, and mark memory blocks in which one or more storage operations have failed as bad blocks. The controller is further configured to identify a pattern of multiple bad blocks occurring over a sequence of multiple consecutive storage operations, the pattern is indicative of a system-level malfunction in a memory system including the controller, and in response to identifying the pattern, to perform a corrective action to the memory system.

Abstract: An example operation may include one or more of connecting, by a transaction manager node, to a blockchain configured to store transaction data, receiving, by the transaction manager node, a transaction from a user node, the transaction includes a transactional operation, performing, by the transaction manager node, the transactional operation on an at least one two-phase commit capable resource, writing, by the transaction manager node, the transaction data into a recovery log, committing, by the transaction manager node, the transaction to the blockchain, and in response to an unknown outcome of the commit of the transaction, executing a recovery operation.

Abstract: An apparatus includes a memory and a hardware processor. The memory stores a plurality of reprocessing rules. The processor receives a request message from a user device. The processor communicates a second request to a first resource and a third request to a second resource. The processor determines that a response to the second request was not received. The processor increases the first timeout. The processor communicates the second request to the first resource after increasing the first timeout, receives a response to the second request, and determines that a response to the third request was not received. The processor increases the reconnect parameter. The processor communicates the third request to the second resource after increasing the reconnect parameter, receives a response to the third request, generates a response message to the request message, and communicates the response message.