Patents Examined by Joseph D Manoskey
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Patent number: 11275639Abstract: The present disclosure provides systems and methods for detecting and correlating anomalous time-series data. A system may receive and process time-series data associated with one or more network data streams to generate sets of aligned time-series data. The system may detect anomalous time-stamped data points in the sets of aligned time series data and generate groups of annotated time-series data. The annotation identifies specific time-stamped data points as anomalous. The system may determine the number of anomalous groups of annotated time-series data within all groups of annotated time-series data and may further determine the probability that one or more anomalous groups belong to at least one of the groups of annotated time-series data using a generative statistical model and outputting one or more correlated anomalous groups. The system may generate a detailed statistical report for each correlated anomalous group and output an aggregated statistical report for the correlated groups.Type: GrantFiled: March 2, 2020Date of Patent: March 15, 2022Assignee: Google LLCInventors: Xiang Wang, Tara Safavi
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Patent number: 11275649Abstract: Methods, computer systems, computer-storage media, and graphical user interfaces are provided for facilitating data error detection, according to embodiments of the present invention. In one embodiment, a target data set having a plurality of values for which to identify incompatible data is obtained. A pattern for each of the plurality of values is generated using at least one generalization language. A pair of patterns that represent a pair of values is utilized to identify a compatibility indicator that corresponds with a pair of training patterns in a compatibility index that match the pair of patterns. The compatibility indicator indicates the pair of patterns are incompatible with one another based on a statistical analysis performed in association with a corpus of data external to the target data set. An indication that the values are incompatible with one another is provided.Type: GrantFiled: January 19, 2018Date of Patent: March 15, 2022Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Yeye He, Huang Zhipeng
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Patent number: 11263078Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.Type: GrantFiled: January 21, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Yoshinori Fujiwara, Vivek Kotti, Christopher G. Wieduwilt, Jason M. Johnson, Kevin G. Werhane
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Patent number: 11256610Abstract: Methods and systems for generating a combined metric parameter for A/B testing comprising: acquiring a respective first metric parameter for a first and second plurality of feature vectors, a combination of the respective first metric parameters being indicative of a direction of a change in user interactions between the control version and the treatment version, acquiring a respective second metric parameter for the first and second plurality of feature vectors, a combination of the respective second metric parameters being indicative of a magnitude of the change in user interactions between the control and treatment version, generating a respective combined control metric parameter for the first plurality of feature vectors and the second plurality of feature vectors, the combination of the respective combined metric parameters being simultaneously indicative of the magnitude and the direction of the change in user interactions between the control and treatment version.Type: GrantFiled: July 14, 2020Date of Patent: February 22, 2022Assignee: YANDEX EUROPE AGInventors: Evgeny Vyacheslavovich Kharitonov, Aleksey Valyerevich Drutsa, Pavel Viktorovich Serdyukov
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Patent number: 11256578Abstract: Techniques for determining one or more replication paths for resources in different failure domains, while maintaining a target resiliency level, are disclosed. A replication path is a sequence of at least a subset of the set of resources. Based on the sequence, a resource is selected for replicating at least a portion of the resource consumers corresponding to each of the subset of resources. A replication path may be determined by adding a resource to the replication path and/or replacing one resource with another resource to modify the replication path. The modified replication path maintains the target resiliency level if the modified replication path does not include any loop of a length less than or equal to the target resiliency level.Type: GrantFiled: April 22, 2020Date of Patent: February 22, 2022Assignee: Oracle International CorporationInventors: Samir Sebbah, Claire M. Bagley
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Patent number: 11249867Abstract: Described herein is a method, system, and non-transitory computer readable medium for helping customers in accessing data through an application from a replica database, detecting whether the replica database, zone of availability of the replica database, or geographical region encompassing the zone of availability is experiencing an outage or other failure, and re-routing traffic to a backup replica database accordingly. To assess the status of the database, metrics are pushed in a secure manner from a private subnet to a public-facing monitoring agent, achieving a clear segregation of private subnet and public facing components. Further, circuit-breaker logic is included for preventing failure during updating DNS addresses during the re-routing process.Type: GrantFiled: May 5, 2020Date of Patent: February 15, 2022Assignee: Capital One Services, LLCInventors: Kasi Reddy Sangala, Shah Sidi, Sampath Kumar Kasilingam, Paul Ly
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Patent number: 11226879Abstract: A computer-implemented method according to one aspect includes determining whether an operating system of a node of a distributed computing environment is functioning correctly by sending a first management query to the node; in response to determining that the operating system of the node is not functioning correctly, determining whether the node has an active communication link by sending a second management query to ports associated with the node; and in response to determining that the node has an active communication link, resetting the active communication link for the node by sending a reset request to the ports associated with the node.Type: GrantFiled: May 8, 2020Date of Patent: January 18, 2022Assignee: International Business Machines CorporationInventors: Constantine Gavrilov, Eli Koren
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Patent number: 11216333Abstract: Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.Type: GrantFiled: September 23, 2019Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Scott E. Schaefer, Aaron P. Boehm
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Patent number: 11210152Abstract: An electronic apparatus is configured to, in a period from returning from an energy-saving mode to determining to change to the energy-saving mode, capture screenshot data every time the first controller circuit detects input from a user into the input device, the screenshot data being data of a screen displayed on the first display device, determine an error code, the error code identifying an error that occurred in the period, and generate a screenshot log and store the screenshot log in the first storage device, the screenshot log including a series of the screenshot data in the period and the error code identifying the error that occurred in the period, receive the screenshot log send request from the error solution information provider apparatus, and then send the screenshot log stored in the first storage device to the error solution information provider apparatus.Type: GrantFiled: March 26, 2020Date of Patent: December 28, 2021Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Tetsuyuki Chimura, Masaaki Aiba, Tomoki Oyasato, Tomoyuki Izumi, Naoki Yoshida
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Patent number: 11204839Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.Type: GrantFiled: February 20, 2020Date of Patent: December 21, 2021Assignee: SK hynix Inc.Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
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Patent number: 11188407Abstract: When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.Type: GrantFiled: May 15, 2019Date of Patent: November 30, 2021Assignee: Amazon Technologies, Inc.Inventors: Robert Charles Swanson, Troy Lawson Bevis, Nathan Pritchard, Christopher James BeSerra
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Patent number: 11188420Abstract: A method addresses a defect in software. The method periodically captures snapshots of versions of code for a particular software program as one or more functionalities are added to the particular software program. The method determines that a current version of the particular software program has a defect, and then iteratively tests previous versions of that particular software program until a most-recent non-defective version of the particular software program is detected. A software developer is directed to either debug the current version of the particular software program, or else re-create the current version of the particular software program from the most-recent non-defective version of the particular software program, depending on which approach is faster.Type: GrantFiled: January 15, 2020Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Zachary A. Silverstein, Samir Nasser, Neil Delima, Shikhar Kwatra
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Patent number: 11182238Abstract: Embodiments are disclosed for problematic characters. The techniques include configuring a sort utility of an operating system to generate a replacement file that resolves a problem of a problematic file. Configuring the sort utility includes identifying the problematic file. The techniques further include identifying the replacement file. Additionally, configuring the sort utility includes providing an input to the sort utility that specifies a problematic character and a replacement character. Also, configuring the sort utility includes generating the replacement file by executing the configured sort utility.Type: GrantFiled: July 16, 2019Date of Patent: November 23, 2021Assignee: International Buusiness Machines CorporationInventor: Priyadarshi Samal
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Patent number: 11182278Abstract: Computer-implemented techniques are provided for in-device real time application program performance feature testing by test devices of an independent test device system of a performance test system. The performance test system includes an access control program that limits access to certain performance data that is automatically generated by the test devices, at test. A client device communicatively coupled to the performance test system via an internetwork installs program instructions of a performance test that may be iteratively executed to test an application program under test (APUT) in a test device. Different test conditions adapted to different performance feature testing identifying result data that is processed to determine the performance feature being tested. A test result is determined based on each performance test iteration and the test result, in addition to other test data is displayed on a user interface.Type: GrantFiled: August 29, 2019Date of Patent: November 23, 2021Assignees: ATLASSIAN PTY LTD., ATLASSIAN INC.Inventor: Nancy Gomez
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Patent number: 11176012Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.Type: GrantFiled: March 18, 2020Date of Patent: November 16, 2021Assignee: Arm LimitedInventors: Emre Ozer, Xabier Iturbe, Balaji Venu
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Patent number: 11163630Abstract: A system and method for reducing execution errors make by a software service are disclosed. The service has several features whose execution paths are switched on or off by corresponding feature toggles, i.e. flags in a configuration database. The performance, and especially error generation, of each feature is monitored automatically and an instantaneous error rate is produced. When the error rate exceeds a given threshold error rate for a particular feature, the corresponding toggle is disabled in the configuration database and the service is triggered to restart using the updated toggles, thereby disabling the problematic feature. The system and method also determine whether the error rate increased due to a transient error condition, such as a data link drop or a secondary service restart, and re-enable the toggle when the error condition has passed.Type: GrantFiled: October 18, 2019Date of Patent: November 2, 2021Assignee: Dell Products L.P.Inventors: Stephen Dunne, Morton Davis Nivers
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Patent number: 11163665Abstract: Utilizing diffgrams for trace indexing and replay. A subset of instructions of a trace, beginning with a first instruction and ending with a second instruction, are replayed to obtain state of one or more named resources. Based on replaying the subset of instructions, a diffgram is generated, which is structured such that addition of the diffgram at the first instruction brings the one or more named resources to the second state, and subtraction of the diffgram at the second instruction brings the one or more named resource to the first state. A pat of reaching a target instruction, the diffgram is later added at the first instruction to restore the second state at the second instruction, or subtracted at the second instruction to restore the first state of the first instruction.Type: GrantFiled: September 17, 2019Date of Patent: November 2, 2021Assignee: Microsoft Technology Licensing, LLCInventor: Jordi Mola
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Patent number: 11163661Abstract: Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.Type: GrantFiled: August 9, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Madhusudan Kadiyala, Narasimha R. Adiga, Manoj Dusanapudi
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Patent number: 11144382Abstract: A computing device and method for profiling and diagnostics in an Internet of Things (IoT) system, including matching an observed solution characteristic of the IoT system to an anomaly in an anomaly database.Type: GrantFiled: December 9, 2019Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Jerin C Justin, Kumar Balasubramanian, Naveen Manicka
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Patent number: 11144381Abstract: Method and system are provided for event relationship analysis in fault management. The method includes: providing a history of a plurality of event instances relating to multiple events identified by event identifiers, where an event instance has one or more event occurrences referencing an event identifier, the history including the event occurrences and resolution event information; analyzing the event occurrences relating to each event identifier to identify a first occurrence(s) of an event instance; analyzing the resolution event information relating to each event identifier to identify any event resolution time for an event instance; comparing two event identifiers to obtain a relationship score between the two event identifiers, wherein the comparing is based on a combination of first occurrences of event instances relating to the two event identifiers and resolution times of the event instances; and creating a group of events that are related based on the relationship scores.Type: GrantFiled: November 22, 2019Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Anthony T. Brew, Jonathan I. Settle