Abstract: An error detecting system, comprising: a control circuit; and a first error detecting circuit, coupled to the control circuit, configure to detect error of input data. The control circuit controls the first error detecting circuit to use a first setting to detect the error in a first time period, controls the first error detecting circuit to use a second setting to detect the error in a second time period following the first time period, and controls the first error detecting circuit to generate a first detecting result corresponding to the first setting and the second setting after the detection corresponding to the first setting and the second setting are completed.

Abstract: A method may include, during a boot of an information handling system, detecting a soft failure associated with a read request to storage media of the information handling system wherein the soft failure is not visible to an operating system of the information handling system and in response to detecting the soft failure, rewriting a sector of the storage media affected by the soft failure to correct the soft failure.

Abstract: A customer may use a disaster recovery service to generate a disaster recovery scenario in order to make certain resources available to the customer in the event of a data region failure. The customer may specify a recovery point objective, a recovery time objective and a recovery data region for the scenario. Accordingly, the disaster recovery service may coordinate with one or more other services provided by the computing resource service provider to reproduce the customer resources and other resources necessary to support the customer resources. These reproduced resources may be transferred to the recovery data region based at least in part on the parameters specified by the customer. In the event of a data region failure, the disaster recovery service may update the domain name system to resolve any customer requests for the customer resources to the recovery data region.

Abstract: A system and method for providing a status indicator during a power-on self-test routine. A basic input output system is operable to execute the power-on self-test routine and output a status of the power-on self-test routine. A plurality of storage devices that each have an externally visible indicator. A controller is coupled to the basic input output system and the plurality of storage devices. The controller is operable to receive the status from the basic input output system and control the externally visible indicator of each of the storage devices in response to the status received from the basic input output system.

Abstract: A failure resistant distributed computing system includes primary and secondary datacenters each comprising a plurality of computerized servers. A control center selects orchestrations from a predefined list and transmits the orchestrations to the datacenters. Transmitted orchestrations include less than all machine-readable actions necessary to execute the orchestrations. The datacenters execute each received orchestration by referencing a full set of actions corresponding to the received orchestration as previously stored or programmed into the computerized server and executing the referenced full set of actions. At least one of the orchestrations comprises a failover operation from the primary datacenter to the secondary datacenter.

Abstract: The present disclosure describes methods, systems, and computer program products for providing additional stack trace information for time-based sampling (TBS) in asynchronous execution environments. One computer-implemented method includes determining whether time-based sampling is activated to capture a time-based sampling data during execution of a JavaScript function; in response to determining that the time-based sampling is activated to capture the time-based sampling data, determining whether a callback stack trace is active; in response to determining that the callback stack trace is active, loading the callback stack trace; retrieving a current stack trace of the JavaScript function; and saving the loaded callback stack trace and the current stack trace of the JavaScript function as the time-based sampling data.

Abstract: An outage detection system identifies a reported incident as a candidate outage incident based upon an input received from a first user of a customer concerning the reported incident; determines whether the candidate outage incident relates to at least a threshold number of prior candidate outage incidents reported by other users; and, if so, associates the candidate outage incident with the prior candidate outage incidents, and identifies the candidate outage incident and the associated prior candidate outage incidents as relating to an outage.

Abstract: Methods, systems, and storage media including instructions for resolving technology issues is described. One of the methods includes receiving, by at least one processor, a session record of user producing a technical error on a computer system. The method includes providing, by the at least one processor, the session record for resolution to a processing system. The method also includes providing, by the at least one processor, a potential solution to the technical error.

Abstract: A method includes receiving an indication of a change to a page of a database and adding a new log record corresponding to the page to a common log comprising log records, the new log record describing the change made to the page and assigned a distinct version number. The method further includes synchronously writing the new log record to each log store replica in a set of log store replicas, and asynchronously writing the new log record to all page store replicas for the page to update the page that is stored on each of the page store replicas, where each store replica for the page serves reads for the page. In response to receiving, from a predetermined number of the page store replicas, an acknowledgement of the writing of the log record, discarding the new log record from the common log.

Abstract: The disclosed technology is generally directed to IoT device update failure recovery. In one example of the technology, after writing an updated release to memory, a determination is made whether the updated release is valid. The updated release includes a plurality of image binaries. If the updated release is determined to be valid, the updated release is made the current release. A determination is made as to whether the current release is stable. Upon determining that the current release is unstable, an auto-rollback is performed. Performing the auto-rollback includes, via at least one processor, automatically: obtaining an uncompressed backup of a previous release; making the uncompressed backup of the previous release the current release; and executing the uncompressed backup.

Abstract: A log analysis device includes a correlation model generation unit that generates a correlation model between a pattern of a log output from a monitored target in a prescribed period and the monitored target, based on time series of the pattern and an operating status of the monitored target, and a determination unit that determines existence of an abnormality in the monitored target based on the correlation model.

Abstract: An image processing device capable of repeatedly sending internal data stored inside the device to a server at a predetermined timing, comprises: a hardware processor that: obtains the internal data from the inside the device at every data transmission timing; determines whether or not to send the latest internal data obtained at the current data transmission timing to the server based on a change in an operation status during a period from the previous data transmission timing to the current data transmission timing; and sends the latest internal data to the server when determining to send the latest internal data to the server.

Abstract: An application checkpoint and recovery system includes an application provided using application information from a first location in a memory fabric. A data mover device receives an application checkpoint instruction and performs application checkpoint operations including capturing a first version of the application information from the first location in the memory fabric, and providing the first version of the application information in a second location in the memory fabric. The data mover device may receive an application recovery instruction subsequent to the application modifying the first version of the application information to provide a second version of the application information in the first location of the memory fabric, and may transfer the first version of the application information from the second location in the memory fabric to the first location in the memory fabric so that it is available for use in providing the application.

Abstract: The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (DVC) disposed on the host computing device, and a virtualized input/output (I/O) device in communication with the DVC.

Abstract: A reliable network function virtualization (rVNF) system includes a virtualized network function (VNF) application instance that includes a plurality of physical VNF instances. A load balancer provides an interface between a client and the VNF application instance. A load balancer interface facilitates delivery of packets related to a particular user context to the same physical VNF instance. A communication interface facilitates communication between the client and the VNF application instance. Application storage stores session data associated with the VNF application instance.

Abstract: A test method for a basic input/output system (BIOS), configured to test a computer device which includes the BIOS when a power on self test (POST) of the BIOS fails, is disclosed including following operations: enabling a fixing function of the BIOS by a debug port of a motherboard of the computer device; enabling a first memory device and disabling a second memory device, by the debug port; according to the fixing function, turning on the computer device by the first memory device; and determining whether the computer device is turned on successfully.

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Abstract: Aspects capture test coverage in a distributed system, wherein a processor instigates execution of a unique hypertext transfer request protocol test case within a distributed system of different, networked servers. The header of the unique test case includes a unique name for the unique test case, and the distributed system servers are each configured to, in response to processing a test case, generate a time-stamped log entry that includes header data for the processed test case and a uniform resource locator address of the processing server. The processor thus maps the unique test case to a subset of the distributed system servers as endpoint servers of the unique test case, in response to determining that the uniform resource locator addresses of each of the subset endpoint servers are listed within generated log entries of the endpoint servers in association with the unique test case name.

Abstract: A processor may identify, using historical data, an amount of computing resources consumed to remedy the failure with an automatic remedy step. The processor may determine that the amount of consumed computing resources to remedy the failure is less than an amount of computing resources consumed by restarting the process. The processor may perform the automatic remedy step. The processor may identify that the automatic remedy step has failed. The processor may determine a waiting period based on an estimated time to receive a user response to the failure and an estimated load on the computing cluster. The processor may display a generated alert to a user during the waiting period. The processor may identify that no user input has been received during the waiting period. The processor may release computing resources corresponding to the process.

Abstract: Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.