Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.

Abstract: An excess loop delay compensation (ELDC) technique for use with a successive approximation register (SAR) based quantizer in a continuous time delta-sigma ADC is described. The techniques can efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers. An ELDC circuit can include a charge pump having a digitally programmable capacitance to adjust a gain, such as the gain of the ELDC digital-to-analog converter (DAC) or the gain of the SAR DAC.

Abstract: A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

Abstract: The present invention relates to an antenna assembly for a beamforming antenna, comprising a reflector and an antenna array that includes a plurality of first radiating elements that are arranged as a first vertically extending array, the first radiating elements extending forwardly from the reflector; and a plurality of second radiating elements that are arranged as a second vertically extending array, the second radiating elements extending forwardly from the reflector. Two adjacent first radiating elements are spaced apart from one another by a first distance, and a first radiating element and an adjacent second radiating element are spaced apart from one another by a second distance. The first distance is substantially equal to the second distance. The antenna assembly further comprises a plurality of parasitic elements that are placed along sides of the first and second of the vertically extending arrays.

Abstract: An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.

Abstract: A broadband dual-polarized antenna integrated high-performance balun. The antenna structure consists of three main parts: radiator, feeding structure and reflector. The radiation element consists of four radiation parts with petal shape, forming two pairs of orthogonal dipole antennas. The feeding structure consists of four circuit boards with separated lines, forming resonant structures corresponding to a balance transformer. The reflector enables to direct the beam, increasing the antenna's orientation.

Abstract: Described herein is an apparatus and method for enhancing the dynamic range of an analog-to-digital converter (ADC). In one embodiment of the present approach, an analog input signal is amplified in a programmable gain amplifier (PGA) before the ADC receives the signal, so that the gain applied to an input signal, and gain (or attenuation) later applied in order to balance the overall gain of the circuit, occurs only in either the analog domain; in the prior art, gain occurs partly in each domain. The ADC gain is then adjusted to compensate for gain of the PGA and balance the overall gain of the circuit. In another embodiment, the ADC gain is adjusted, and gain of a digital gain element that receives the signal from the ADC is adjusted to compensate for the ADC gain and balance the overall gain of the circuit, eliminating the need for a PGA.

Abstract: A method, computer program, and computer system is provided for coding video data. Video data including one or more reference locations is received. The one or more reference locations are updated in a history list associated with the received video data based on intra block copy for a single value string mode. The video data is decoded based on the updated reference locations.

Abstract: Techniques are provided for improving the performance of a multi-band antenna in a wireless device. An example wireless device includes at least one radio frequency integrated circuit, and at least one patch antenna operably coupled to the at least one radio frequency integrated circuit, including a first patch operably coupled to the at least one radio frequency integrated circuit, a ground plane disposed below the first patch, and a plurality of via wall structures disposed around the first patch, wherein each of the plurality of via wall structures is electrically coupled to the ground plane.

Abstract: An automobile antenna assembly including a housing adapted for installation on a roof of an automobile, the housing having a base portion and a fin portion extending from the base portion, a radio antenna disposed within the fin portion, and a photo radiation intensity sensor disposed within the base portion, the photo radiation intensity sensor including a first light detecting element located on a first side of the fin portion and a second light detecting element located on a second side of the fin portion opposite the first side, wherein at least a portion of the base portion is translucent for allowing light to be received by the first and second light detecting elements, the fin portion providing a light barrier between the first light detecting element and the second light detecting element.

Abstract: An electronic device including an antenna and a conductive pattern formed around the antenna is provided.

Abstract: An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).

Abstract: Disclosed is a radiator assembly configured to operate in the range of 3.4-4.2 GHz. The radiator assembly comprises a folded dipole with four dipole arms that radiate in two orthogonal polarization planes, whereby the signal of each polarization orientation is radiated by two opposite radiator arms that radiate the signal 180 degrees out of phase from each other. The radiator assembly has a balun structure that includes a balun trace that conductively couples to a ground element on the same side of the balun stem plate. The combination of the shape of the folded dipole and the balun structure reduces cross polarization between the two polarization states and maintains strong phase control between the opposing radiator arms.

Abstract: A dual-polarized antenna and a dual-polarized antenna assembly including the same are provided. A dual-polarized antenna includes a base board, feeding unit supported on the base board, and radiation plate supported on the feeding unit. The feeding unit includes a first and a second feeding boards arranged to cross each other on the base board. The first feeding board includes a first feed line configured to supply a first reference-phase signal to a first point on the radiation plate and supply a first antiphase signal having an antiphase relative to the first reference-phase signal to a second point on the radiation plate. The second feeding board includes a second feed line configured to supply a second reference-phase signal to a third point on the radiation plate and supply a second antiphase signal having an antiphase relative to the second reference-phase signal to a fourth point on the radiation plate.

Abstract: A dual-polarized radiating element for a base station antenna includes a first dipole that extends along a first axis, the first dipole including a first dipole arm and a second dipole arm and a second dipole that extends along a second axis, the second dipole including a third dipole arm and a fourth dipole arm and the second axis being generally perpendicular to the first axis, where each of the first through fourth dipole arms has first and second spaced-apart conductive segments that together form a generally oval shape.

Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

Abstract: A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (Ntm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.

Abstract: A data output method, a data acquisition method, a device, and an electronic apparatus are provided, and a specific technical solution is: reading a first data sub-block, and splicing the first data sub-block into a continuous data stream, wherein the first data sub-block is a data sub-block in transferred data in a neural network; compressing the continuous data stream to acquire a second data sub-block; determining, according to a length of the first data sub-block and a length of the second data sub-block, whether there is a gain in compression of the continuous data stream; outputting the second data sub-block if there is the gain in the compression of the continuous data stream.

Abstract: The present invention relates to a base station antenna. The base station antenna comprises: a reflector that is configured to provide a ground plane; a first radiating element array including at least one first cross-polarized radiating element that is arranged on the reflector; and a first parasitic element array including first through third parasitic element pairs, wherein each of the first through third parasitic element pairs includes a pair of parasitic elements that are arranged substantially symmetrically on both sides of the first longitudinal axis, and distances from the first through third parasitic element pairs respectively to the first longitudinal axis increase sequentially, wherein projections of any two of the first parasitic element pair, the second parasitic element pair, the third parasitic element pair, and the at least one first cross-polarized radiating element on the first longitudinal axis at least partly overlap.

Abstract: A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.