Abstract: Embodiments of the disclosure provide improved mechanisms for applying DEM techniques to a DAC comprising a plurality of cells. Disclosed mechanisms include keeping track of the amplitude of input digital signal over a certain time period to determine a range of amplitudes of a portion of the input signal, and, when converting the digital values of that portion to analog values and applying a particular DEM technique, limiting the number of DAC cells on which a DEM technique is applied only to a number that is necessary for generating the analog output corresponding to the tracked portion, which number is determined based on the tracked amplitudes and could be smaller than the total number of DAC cells. In this manner, mismatch error may be reduced for smaller input signal amplitudes. Whenever possible, unused DAC cells may be put into a power saving mode, providing the advantage of reduced power consumption.

Abstract: A voltage regulator, which contains a circuit to determine its output power. It has an output node providing an output voltage for a load; current sensing means for sensing an output current flowing at the output node; voltage providing means for providing a digital representation of the output voltage or of an input voltage to the voltage regulator; output power determination means comprising a digitally controllable variable resistance circuit receiving the digital voltage representation from the voltage providing means and generating a resistance, wherein the variable resistance circuit is connected to the current sensing means to obtain a signal that depends upon the output current and generates a voltage depending on the generated resistance and the obtained signal; and the output power determining means are adapted to determine the output power of the voltage regulator based on the voltage generated by the variable resistance circuit.

Abstract: A method and an apparatus for a reconfigurable antenna are provided. The apparatus is a reconfigurable antenna including a patch antenna and one or more parasitic slots. The patch antenna includes a first conductor plane and a second conductor plane. The second conductor plane is configured to provide a ground plane for the first conductor plane. The reconfigurable antenna further includes a first parasitic slot of the one or more parasitic slots formed in the second conductor plane. The first parasitic slot of the one or more parasitic slots is formed by a first set of two opposing portions of the second conductor plane. The first set of two opposing portions is separated by a first cutout in the second conductor plane. The reconfigurable antenna further includes a first switch configured to enable or disable the first parasitic slot of the one or more parasitic slots.

Abstract: An antenna on a sapphire structure. The antenna includes a sapphire structure having a first side, and a second side positioned opposite the first side. The antenna also includes a first antenna trace positioned on the first side of the sapphire structure, and a second antenna trace positioned on the second side of the sapphire structure. Additionally, the antenna includes at least one via formed through the sapphire structure. The at least one via electrically connects the first antenna trace to the second antenna trace.

Abstract: A method and a digital-to-analog converter (DAC) circuit involve forming an analog signal using charge sharing operations. The DAC circuit includes a plurality of digital components with associated parasitic capacitances. The digital components are activated based on a digital input code, such that charge is shared among the parasitic capacitances to form a first analog signal proportional to the digital input code. The digital components can also be activated based on a complementary code to form a second analog signal. The first analog signal and the second analog signal can be used to form, as a final output of the DAC circuit, an analog signal that is linearly proportional to the digital input code.

Abstract: This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking device or other computing apparatus. Each data unit in the group may only have values for fields in a master set. The described systems are particularly suited for hardware-level processing of groups of sparsely-populated data units, in which a large number of the data units have values for only a small number of the fields. In an embodiment, non-value carrying fields in a data unit are compressed based on a compression profile selected for the data unit. The compression profile indicates, for each master field, whether the compressed data unit includes a value for that field. Non-value carrying fields are omitted from the compressed data unit. The compression profile also permits compression of value-carrying fields using variable-width field lengths specified in the profile.

Abstract: Methods and apparatuses for generating match data for a symbol in a symbol history for use in a hardware-based data compressor. An apparatus for performing history matching for Lempel-Ziv (“LZ”) compression includes a symbol history RAM comprising 2S N bit entries, each entry corresponding to a symbol value represented by S bits and indicating locations within the last N symbols of input data where the symbol value occurred; a symbol counter array comprising 2S counters, each counter corresponding to a symbol value and indicating a number of symbols processed since the last occurrence of the symbol value in the input data; and a barrel shifter configured to shift the entry corresponding to an input symbol value left by a number of bits based on a value of the counter corresponding to the input symbol value to produce a symbol match vector for the input symbol.

Abstract: A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents.

Abstract: An object of the present invention is to provide a cellular telephone terminal in which intuitive operation is possible, by providing a rotary dial portion. A cellular telephone terminal is provided with: a body that includes an operation unit side body, a display part side body, and a hinge mechanism that connects the operation unit side body g and the display part side body; a rotary dial portion, which is rotatable around a rotational axis, and which is attached to the body with a standard position; a mark which serves as an indicator for a rotation amount of the rotary dial portion; and a control part that causes one application among a plurality of applications to enter a state in which activation thereof is possible, based on the rotation amount of the rotary dial portion.

Abstract: Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

Abstract: Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive Approximation Register (SAR) to provide digital approximations of an input analog voltage to a Capacitor Digital-to-Analog Converter (DAC), which generates a voltage from the digital approximations. The two voltages are compared and the comparison value used as the input for the SAR. After successive approximations, a digital combiner generates the digital conversion value from the outputs of the Flash-assisted ADC and the SAR. In one aspect, the bit cycles required for conversion are reduced by using redundancy and recombination.

Abstract: An information processing apparatus receives a compressed file in which character string data with a first character code is compressed by a unit of character string including a single character or a plurality of characters. The information processing apparatus converts compression information included in the compressed file into converted compression information, the compression information mapping each of compressed character string data in the compressed file to each of corresponding unit of character string with the first character code, thereby the converted compression information mapping each of the compressed character string data in the compressed file to each of the corresponding unit of character string with a second character code. The information processing apparatus generates a converted compression file from the converted compression information and each of the compressed character string data.

Abstract: An absolute encoder includes a scale with a plurality of marks of various types arranged with a space and a period. A detector includes a plurality of elements arranged along a direction corresponding to the aforementioned arrangement, and detects a partial plurality of marks. A signal processor performs amplitude quantization with respect to each period of periodic signals with a plurality of periods output from the detector to generate a data string. First position data having a resolution of the period is generated. The signal processor obtains a plurality of thresholds for the quantization respectively corresponding to a plurality of periodic signals of the periodic signals with the plurality of periods based on a plurality of representative values respectively obtained from the periodic signals with the plurality of periods.

Abstract: A system, circuit and method for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal are disclosed. For example, a circuit for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal is disclosed. The circuit includes a comparator configured to receive a differential voltage signal including a high common mode voltage component, and output a digital signal associated with the differential voltage signal. The circuit also includes a level shifter configured to receive the digital signal and shift the level of the digital signal to a low level, and an integrator configured to receive the digital low level signal and output a ramping voltage associated with the low level signal. Furthermore, the circuit includes an analog-to-digital converter configured to receive the ramping voltage and output a digital bit-stream associated with the ramping voltage.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract: A robust and fast background calibration technique for correction of time-interleaved ADC offset, gain, bandwidth, and timing mismatches is proposed. The technique combines the use of a calibration signal and a reference ADC. The calibration signal enhances robustness and makes the technique independent of the input signal's statistics. The reference ADC speeds up convergence and enables the use of a small amplitude calibration signal that does not significantly reduce the input signal dynamic range. The calibration signal can be subtracted or filtered from the ADC output and is therefore invisible to the ADC user.