Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Abstract: A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data.

Abstract: A method of encoding data into a chain reaction code includes generating a set of input symbols from input data. Subsequently, one or more non-systematic output symbols is generated from the set of input symbols, each of the one or more non-systematic output symbols being selected from an alphabet of non-systematic output symbols, and each non-systematic output symbol generated as a function of one or more of the input symbols. As a result of this encoding process, any subset of the set of input symbols is recoverable from (i) a predetermined number of non-systematic output symbols, or (ii) a combination of (a) input symbols which are not included in the subset of input symbols that are to be recovered, and (b) one or more of the non-systematic output symbols.

Abstract: A method is disclosed. An analog signal is sampled to form a sample value using a sample and hold circuit. The sample value is converted to form a first digital result. The sample value is converted to form a second digital result.

Abstract: A method for decoding includes receiving channel inputs for respective bits of a super code word that includes at least first and second component code words having a shared group of bits. At least the first and second component code words are iteratively decoded, and, in response to recognizing that the first and second component code words contain errors only within the shared group of bits, the first and second component code words are jointly decoded.

Abstract: A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal.

Abstract: A dielectric resonator oscillator includes a dielectric resonator; a transmission line disposed adjacent the dielectric resonator; an active device having an input electrically connected to the transmission line; a matching network having an input electrically connected to an output of the active device and an output configured to be connected to a load; wherein both the transmission line and the active device are positioned sufficiently close to the dielectric resonator to form part of a resonant circuit with the dielectric resonator.

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Abstract: For boosting decompression in the presence of reoccurring Huffman trees, a previous Huffman tree is used to decompress a new data block if a match is identified between a compacted description of the Huffman tree and a recently used Huffman tree compaction.

Abstract: An antenna on a sapphire structure. The antenna includes a sapphire structure having a first side, and a second side positioned opposite the first side. The antenna also includes a first antenna trace positioned on the first side of the sapphire structure, and a second antenna trace positioned on the second side of the sapphire structure. Additionally, the antenna includes at least one via formed through the sapphire structure. The at least one via electrically connects the first antenna trace to the second antenna trace.

Abstract: In a DAC device, a distortion correction function g1(x) of a harmonic obtained from a result of a frequency analysis on an analog output signal of a DAC circuit is obtained. A correction value is determined based on the correction function g1(x) in accordance with an input digital signal, and is previously stored in a memory. A nonlinear correction circuit reads a corresponding correction value from the memory in accordance with the value of a digital signal output from a digital filter, and transmits the correction value to a subtractor. The subtractor subtracts the correction value from the digital signal output from the digital filter.

Abstract: The application disclose a sigma-delta analog-to-digital converter.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including: a first signal path including a first sample and hold circuit responsive to an input signal for sampling the input signal at a first resolution; a second signal path arranged parallel to the first signal path and including a second sample and hold circuit responsive to the input signal for sampling the input signal at a second resolution; and a control circuit arranged in series with the first and second signal paths and configured to isolate one of the first and second signal paths from an output of the control circuit in response to a control signal.

Abstract: The present invention generally relates to storing sequence read data. The invention can involve obtaining a plurality of sequence reads from a sample, identifying one or more sets of duplicative sequence reads within the plurality of sequence reads, and storing only one of the sequence reads from each set of duplicative sequence reads in a text file using nucleotide characters.

Abstract: A flash analog to digital converter (ADC) provides a temperature compensated trim current by applying a first temperature compensated reference current across a replica resistor ladder. The reference current is mirrored to a trim digital to analog converter, which outputs a fractional portion of the temperature compensated reference current. The proportional trim current is then fed back to the reference current to provide a trimmed temperature compensated reference current. The trimmed reference current is mirrored across the output resistor ladder providing a trimmed current in which the trim varies along with temperature changes due to the trim current being a proportion of the temperature compensated reference current. A proportional trim current which varies with temperature changes is applied to the gain current trim and mismatch current trim in a DAC of a quantizing stage of a sub-ranging ADC.

Abstract: An electronic timepiece has a tubular outside case of which at least part is a conductive material, a transparent crystal, a dial housed in the outside case, an annular antenna body disposed around the dial, a feed part that feeds the antenna body, and a dial ring made of a non-conductive material covering the antenna body. The antenna body includes an annular dielectric base, and an arc-shaped fed element feed by the feed part, an annular parasitic element disposed between the dial ring and crystal, and receives circularly polarized waves.

Abstract: A method for encoding a reduced polar code is disclosed. The method generally includes (a) modifying an input codeword including polar code encoded input data by removing one or more bits from one of (i) a first part of the input codeword and (ii) a second part of the input codeword and (b) generating an output codeword by concatenating the first and the second parts of the modified input codeword.

Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.