Abstract: Data compression systems, methods, and computer program products are disclosed. For each successive input word of an input stream, it is determined whether the input word matches an entry in a lookback table. The lookback table is updated in response to the input word. Input words may be of a number of data types, including zero runs and full or partial matches with an entry in the lookback table. A codeword is generated by entropy encoding a data type corresponding to the input word. The lookback table may be indexed by the position of the input word in the input stream.

Abstract: Analog front-end circuits and methods for configuring analog front-end circuits to improve accuracy of optical pulse energy digitizers are disclosed. More specifically, an analog front-end circuit in accordance with the inventive concepts disclosed herein may be configured to reduce a pulse repetition rate as early in the front-end circuit as possible. It is contemplated that reducing the repetition rate in this manner provides more process time that may be allocated for data acquisition, hold, dump, or time guard bands, all of which may help to improve the measurement accuracy of the analog front-end circuit.

Abstract: The invention relates to a portable electronic device comprising a supporting member receiving on one side conductive contact lands or tracks extending substantially as far as the edge of the side and connecting an electronic microcircuit, the conductive contact lands or tracks comprising a plurality of perforations. The device is noteworthy in that the interior of the perforations is free, or intended to be kept free, of metal.

Abstract: A signal processing apparatus is described comprising a sampling time control circuit configured to provide a sequence of digital values, each digital value specifying a sampling time of a sequence of sampling times, a sampling circuit configured to sample an input signal according to the sequence of sampling times to generate a sampling value of the input signal for each sampling time of the sequence of sampling times and a processing circuit configured to receive the sampling values and configured to process the sampling values based on the sampling times, wherein the sampling time control circuit is configured to introduce jitter into the sampling times, by varying the time intervals between adjacent sampling times.

Abstract: An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern.

Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract: A Segmented Voltage Continuous-Time Digital-to-Analog Converter is disclosed which provides the benefits of segmentation while minimizing the associated disadvantages. The segmented digital to analog converter disclosed here features, in particular, inherent monotonicity and low transition glitches. The segmentation technique is based on coupling an array of switchable current sources and at least one current divider into a resistor string, providing, at least, three levels of segmentation.

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.

Abstract: Disclosed is an antenna in which certain radiators are shared for multiple frequency bands. The antenna may include at least one first radiator for a first frequency band; one or more second radiator for a second frequency band; and a third radiator. Here, the third radiator may be used when realizing the first frequency band and may also be used when realizing the second frequency band.

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

Abstract: The present invention generally relates to storing sequence read data. The invention can involve obtaining a plurality of sequence reads from a sample, identifying one or more sets of duplicative sequence reads within the plurality of sequence reads, and storing only one of the sequence reads from each set of duplicative sequence reads in a text file using nucleotide characters.

Abstract: A method of providing a wide range of input currents for an analog to digital converter (ADC), the method constituted of: receiving an input current; selecting one of a plurality of selectable ratios; and generating at least one sense current, the magnitudes of the at least one generated sense current and the received input current exhibiting the selected ratio, wherein the ADC is arranged to receive a voltage representation of the at least one generated sense current.

Abstract: An A/D converter includes a delta-sigma processing circuit for A/D conversion by delta-sigma modulation, and a cyclic processing circuit for A/D conversion by cyclic processing of amplification of a residue generated in the A/D conversion. The A/D converter further includes a quantization part for outputting a quantized value of quantized output of the delta-sigma processing circuit and a quantized output of the cyclic processing circuit, and a control circuit for generating an A/D conversion result and switching over a reference voltage based on the quantized value. The delta-sigma processing circuit and the cyclic processing circuit include a sampling capacitor, an integration capacitor and a capacitive D/A converter, which includes a DAC capacitor and add and subtract a charge corresponding to a reference voltage to and from a residue of quantization. The sampling capacitor, the DAC capacitor and the integration capacitor are provided as electrically separate capacitors.

Abstract: A method is provided for generating a digital signal from an analog signal generated using a frequency converter on the basis of pulse width modulation with a variable period duration, values of the digital signal corresponding to an average value of the analog signal over an associated period duration of the pulse width modulation.

Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.

Abstract: Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter.

Abstract: A wrist-worn electronic device comprises a housing, a display, a location determining element, a first antenna, and second antenna. The housing includes a lower surface configured to contact a wearer's wrist, an opposing upper surface, and an internal cavity. The display is visible from the upper surface of the housing. The location determining element is configured to process a location signal to determine a current geolocation of the electronic device. The first antenna is positioned on the upper surface of the housing adjacent a perimeter of the display and electrically connected with the second antenna positioned at least partially within the internal cavity. The first antenna and second antenna function in cooperation to receive the location signal from a satellite-based positioning system and communicate the location signal to the location determining element.

Abstract: An encoding system analyzes a data file to determine if portions of the data file include significant disparities in symbol probability. Huffman coding trees are produced for each of the portions of the data file and the portions are separately encoded according to specific Huffman coding trees. Encoded portions and the corresponding Huffman coding tree are packaged together and transmitted to a decoder. The encoder and decoder processes portions using different Huffman coding trees in parallel via multiple processors or processing cores.

Abstract: The invention relates to a radio frequency device including an antenna connected to a capacitor. Said capacitor includes first and second conductive plates that are opposite each other and separated by an insulator. At least one of said first and second plates is formed of a plurality of wire capacitor portions. Said radio frequency device is different in that the antenna and at least one capacitor plate are formed with wire portions placed on a substrate in a guided manner.