Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.

Abstract: The invention of this application is a field-effect transistor type light-emitting device having an electron injection electrode, i.e. a source electrode, a hole injection electrode, i.e. a drain electrode, an emission active member disposed between the source electrode and the drain electrode so as to contact with both electrodes, and a field application electrode, i.e. a gate electrode, for inducing electrons and holes in the emission active member, which is disposed in the vicinity of the emission active member via an electrically insulating member or an insulation gap. The emission active member is made of an inorganic semiconductor material having both an electron transporting property and a hole transporting property.

Abstract: A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

Abstract: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract: A light-emitting diode system (1) comprising at least one light-emitting diode component (2), in which a light-emitting diode chip is arranged in a light-emitting diode housing (21) on a heat sink (22) which can be thermally connected at the rear side (25) of the light-emitting diode housing (21). A carrier plate (3) having a front side (34) and a rear side (31) and a hole for receiving the light-emitting diode component (2) is provided. The light-emitting diode component (2) projects into the hole from the rear side (31) of the carrier plate (3). An electrically insulating thermal connection layer (5) is applied at the rear side (31) of the carrier plate (3), said thermal connection layer being thermally conductively connected to the heat sink (22). A method for producing a light-emitting diode system is also described.

Abstract: A light-emitting device includes an active region that is configured to emit light responsive to a voltage applied thereto. A first encapsulation layer at least partially encapsulates the active region and includes a matrix material and nanoparticles, which modify at least one physical property of the first encapsulation layer. A second encapsulation layer at least partially encapsulates the first encapsulation layer.

Abstract: A modularly constructed electrical component having a module substrate, preferably, of Si, and having one or more preferably un-housed chips placed on the module substrate while being electrically connected thereto and each joined to the module substrate, e.g., by direct wafer bonding. A recess is provided in the module substrate so that a closed hollow space is formed when the chip is joined to the module substrate. The hollow space is not formed by a protective cap, which surrounds the chip and, with the module substrate, closes it on all sides. Rather it is formed by the joining of opposing contact areas of the chip underside and of the upper side of the module substrate. The component can be economically produced because it does not require a protective cap for creating the hollow space. The component has a higher yield than monolithic integration of the functional units.

Abstract: A mounting structure for an IC tag where an IC chip for mounting (10) is mounted so as to be electrically connected to antenna patterns (44a), (44b). The assembly process that mounts the IC chip for mounting (10) on the antenna patterns (44a), (44b) is simplified, which makes it possible to reduce the manufacturing cost of IC tags. The IC chip for mounting 10 is formed by winding conductive wires (12a), (12b) so as to encircle an outer surface of an IC chip (20) between two opposite edges of the IC chip (20) in a state where the conductive wires (12a), (12b) mechanically contact electrodes formed on the IC chip (20) and are electrically connected to the electrodes, so that the IC chip for mounting (10) is joined to the antenna patterns (44a), (44b) via the conductive wires (12a), (12b).

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: There is provided a method in which a TFT with superior electrical characteristics is manufactured and a high performance semiconductor device is realized by assembling a circuit with the TFT. The method of manufacturing the semiconductor device includes: a step of forming a crystal-containing semiconductor film by carrying out a thermal annealing to a semiconductor film; a step of carrying out an oxidizing treatment to the crystal-containing semiconductor film; a step of carrying out a laser annealing treatment to the crystal-containing semiconductor film after the oxidizing treatment has been carried out; and a step of carrying out a furnace annealing treatment to the crystal-containing semiconductor film after the laser annealing. The laser annealing treatment is carried out with an energy density of 250 to 5000 mJ/cm2.

Abstract: Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.

Abstract: The invention relates to a side-emitting LED package and a manufacturing method thereof. The side-emitting LED package includes a substrate with an electrode formed thereon, and a light source disposed on the substrate and electrically connected to the electrode. The side-emitting LED package also includes a molded part having an upper surface with a center thereof depressed concavely, covering and protecting the substrate and the light source, and a reflection layer covering an entire upper surface of the molded part to reflect light sideward from the molded part which forms a light transmitting surface. The package is not restricted in the shape of the molded part and is not affected by the LED chip size, enabling a compact structure. The invention can also process a substrate by a PCB process, enabling mass-production.

Abstract: In a semiconductor device 100, a light emitting device 102 is mounted on a substrate 101. A light reflection preventing film 130 for preventing a reflection of a light is formed on an upper surface of the light emitting device 102. Moreover, a plate-shaped cover 103 formed of a glass having a light transparency is disposed above the light emitting device 102, and a light reflection preventing film 140 for preventing a reflection of a light is also formed on an upper surface of the cover 103.

Abstract: A semiconductor light emitting unit is provided which comprises: a support 1 formed with longitudinal side walls 15 disposed opposite to each other for forming a pair of light reflective surfaces 9, and a bottom wall 16 connected to longitudinal side walls 15 for forming a mount surface 3a between light reflective surfaces 9 to form a channel 3 by longitudinal side walls 15 and bottom wall 16 above mount surface 3a. Formed at either end of channel 3 in the longitudinal direction of support 1 is a vertical opening 18 which serves to directly communicate channels 3 of adjacent light emitting units when plural semiconductor light emitting units are lengthwise arranged, so that there is no lateral side wall 15 obstructing path of light radiated from LED chips 2 toward outside to thereby irradiate uniform light to outside along the longitudinal direction of linear light source.

Abstract: Methods and apparatus for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: An nitride semiconductor device for the improvement of lower operational voltage or increased emitting output, comprises an active layer comprising quantum well layer or layers and barrier layer or layers between n-type nitride, semiconductor layers and p-type nitride semiconductor layers, wherein said quantum layer in said active layer comprises InxGa1—xN (0<x<1) having a peak wavelength of 450 to 540 nm and said active layer comprises laminating layers of 9 to 13, in which at most 3 layers from the side of said n-type nitride semiconductor layers are doped with an n-type impurity selected from the group consisting of Si, Ge and Sn in a range of 5×1016 to 2×1018/cm3.