Abstract: A method and system are disclosed for a high current electrical switch. The switch may be suitable for switching, rectifying or blocking direct current in the range of one to a thousand amperes per module or assembly. It does so with such high efficiency that it produces relatively insignificant heat; such that it requires little or no cooling by convection or radiation. The relatively low heat that is generated in the process is conducted away quite effectively by the electric cables connected to the device.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.

Abstract: A light emitting diode (LED) and a method are provided for fabricating the a LED with an improved structure for better light emitting efficiency and better light output performance.

Abstract: Semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone.

Abstract: A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Abstract: A semiconductor device package is provided which can achieve speeding-up thereof. The semiconductor device package includes: a board which has at least one of a ground plane and a power plane; at least one connecting conductor portion which is formed on an inner wall surface of an opening portion of the board and electrically connected to the corresponding plane; at least one bonding pattern which is formed on a front surface layer portion of the board in the vicinity of an edge of the opening portion, and connected to the corresponding connecting conductor portion; and a second external connection portion which is formed on the side of the front surface layer of the board, and electrically connected to the corresponding plane, respectively, through a through-hole conductor portion formed in the board.

Abstract: According to one aspect of the invention, a polymer device and a method of constructing a polymer device are provided. The polymer device includes a first conductor, a second conductor, and a polymeric body between the first and second conductors. The polymeric body includes a polymer material and a phyllosilicate material.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: A high power LED comprises a substrate. An N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially deposited on the substrate. A semi-insulator layer or a non-N-type semiconductor layer can be interposed between the N-type semiconductor layer and substrate. At least one N-type electrode is connected to the N-type semiconductor layer and is exposed to an opening of the active layer and P-type semiconductor layer. The N-type electrode with a centralized pattern is formed on the middle of the LED. Furthermore, at least one P-type electrode is coupled to the P-type semiconductor layer. The P-type electrode is arranged like a closed ring or an open ring surrounding the N-type electrode. Therefore, the distribution of current paths is dispersed, and illumination areas are simultaneously uniform.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying the first surface of the microelectronic element, and conductive protrusions overlying the compliant layer and projecting away from the first surface of the microelectronic element, wherein the conductive protrusions are electrically interconnected with the contacts of the microelectronic element. The conductive protrusions are movable relative to said microelectronic element.

Abstract: A semiconductor laser device aimed to be reduced in size and that can maintain high position accuracy, and a fabrication method of such a semiconductor laser device are achieved. A semiconductor laser device includes a stem as a base member, and a cap member. The stem includes a main unit having a reference plane, and a heat sink platform as an element mount unit, located on the reference plane for mounting a laser element. The cap member is set on the reference plane of the stem so as to cover the heat sink platform. A hole is formed at the sidewall of the cap member facing the heat sink platform. Fixation between the cap member and the stem is established by fixedly attaching the portion at the inner side of the sidewall of the cap member adjacent the hole to the outer circumferential plane of a heat sink platform.

Abstract: In order to make it possible to easily detect an electrical defect by using an array tester, the present inspection substrate includes: plural scan lines and plural signal lines; plural storage capacitor lines arranged in parallel to the scan lines; storage capacitor elements, each of which uses a part of the storage capacitor line as one of electrodes thereof; storage capacitor upper electrodes formed of the same layer as that for the signal lines and electrically connected to the storage capacitor elements; switching elements arranged on intersection points of the signal lines and the scan lines and electrically connected to the storage capacitor elements; and dummy wiring lines formed by use of at least one of two types of metals constituting electrodes of the switching elements, and electrically connected to any of the scan lines, the signal lines, the storage capacitor lines and the storage capacitor upper electrodes.

Abstract: After the attachment process, a substrate etching process, in which the outer surfaces of the upper and lower substrates are etched to reduce the thickness of the substrates, is performed according to the desired lightening of the substrate. However, since a main seal pattern can be damaged during the substrate etching process, a method of preventing the damage, in which a sub-seal pattern is formed, is suggested. However, if a plurality of unit liquid crystal cells is formed on one substrate, deterioration resulting from a low margin for the sub-seal patterns can occur so that a yield is decreased. In an embodiment according to the present invention, damage of the main seal pattern from the etching solution during the substrate etching process is prevented by the formation of the sub-seal patterns in the exterior of the main seal pattern, and air of the cell interior are easily vented due to the air vent portion having a proper seal pattern for ventilation.

Abstract: A semiconductor light emitting device includes a semiconductor light emitting portion having a first contact layer of a first conductivity, a second contact layer of a second conductivity and an active layer sandwiched between the first and second contact layers. The device further includes a transparent electrode which substantially entirely covers a surface of the second contact layer in ohmic contact with the surface of the second contact layer and is transparent to a wavelength of light emitted from the semiconductor light emitting portion, and a metal reflection film which is opposed to substantially the entire surface of the transparent electrode and electrically connected to the transparent electrode, and reflects the light emitted from the semiconductor light emitting portion and passing through the transparent electrode toward the semiconductor light emitting portion.

Abstract: The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via the filling (6) of a body trench (5) to a highly doped substrate (2) via a conductive connection (15).

Abstract: The invention relates to a photocathode having a structure that permits a decrease in the radiant sensitivity at low temperatures is suppressed so that the S/N ratio is improved. In the photocathode, a light absorbing layer is formed on the upper layer of a substrate. An electron emitting layer is formed on the upper layer of the light absorbing layer. A contact layer having a striped-shape is formed on the upper layer of the electron emitting layer. A surface electrode composed of metal is formed on the surface of the contact layer. The interval between bars in the contact layer is adjusted so as to become 0.2 ?m or more but 2 ?m or less.

Abstract: A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. Luminescent ceramic layers according to embodiments of the invention may be more robust and less sensitive to temperature than prior art phosphor layers. In addition, luminescent ceramics may exhibit less scattering and may therefore increase the conversion efficiency over prior art phosphor layers.