Abstract: A test apparatus and method for design verification of at least one microprocessor chip includes a compatible Joint Task Action Group (JTAG) terminal for access to a plurality of computer functional units contained in the chip. A test input terminal included in the JTAG terminal receives a scan string, the string being coupled to each computer functional unit through a first multiplexer. The scan input string is separated by the JTAG terminal under program control into a series of dedicated scan strings, each dedicated scan string being supplied to a selected functional unit through the first multiplexer. Each functional unit includes start and stop scan clocks for testing the functional under program control using the dedicated scan train for the functional unit. A test output terminal included in the JTAG terminal is coupled to each functional unit through a second multiplexer.

Abstract: A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.

Abstract: An intelligent status monitoring, reporting and control module is coupled to a SCSI bus that interconnects a cluster of SCSI-compatible data storage modules (e.g., magnetic disk drives). The status monitoring, reporting and control module is otherwise coupled to the cluster of SCSI-compatible data storage modules and to power maintenance and/or other maintenance subsystems of the cluster for monitoring and controlling states of the data storage modules and power maintenance and/or other maintenance subsystems that are not readily monitored or controlled directly by way of the SCSI bus. The status monitoring, reporting and control module sends status reports to a local or remote system supervisor and executes control commands supplied by the local or remote system supervisor. The status reports include reports about system temperature and power conditions. The executable commands include commands for regulating system temperature and power conditions.

Abstract: Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing element. The controllers provide input/output processings for the computing elements, as well as monitor their operations to detect errors, and control operation of the computing elements in response to the detected errors.

Abstract: A recovery method and fail-over switch for use in a data storage system in which a plurality of data storage devices are connected to each of two communication paths. The switch may route requests to either of the two communication paths. Switching may be accomplished by two fail-over switches connected to each other and each in connection with one of the two communication paths. With one data storage controller in communication with the data storage devices over a first path and a second data storage controller in communication with the data storage devices over a second path, the fail-over switches may be used upon detection of a malfunction on one path to switch a controller into connection with the remaining operable path so as to share that path with the other controller.

Abstract: The present invention, generally speaking, provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs "envoys" that exhibit the security robustness of prior-art proxies and the transparency and ease-of-use of prior-art packet filters, combining the best of both worlds. No traffic can pass through the firewall unless the firewall has established an envoy for that traffic. Both connection-oriented (e.g., TCP) and connectionless (e.g., UDP-based) services may be handled using envoys. Establishment of an envoy may be subjected to a myriad of tests to "qualify" the user, the requested communication, or both. Therefore, a high level of security may be achieved. The usual added burden of prior-art proxy systems is avoided in such a way as to achieve fall transparency-the user can use standard applications and need not even know of the existence of the firewall. To achieve full transparency, the firewall is configured as two or more sets of virtual hosts.

Abstract: Test data is set in the flip-flop of a test circuit via a scan path in the test mode. A timing converting section forms a plurality of update signals of different timings in the test mode. A multiplexer formed in the test circuit selects one update signal from the plurality of update signals according to a timing converting signal stored in a register. The test data set in the flip-flop is supplied to the internal circuit at a timing defined by the selected update signal. That is, the update signal and timing converting signal are used to control the input timing of test data supplied to the internal circuit for each test circuit.

Abstract: A trailer microprocessor in a debugging tool runs code a known number of cycles behind a master and shadow pair of processors. A pipeline queues up bus activity from the shadow processor a number of cycles, and then outputs those signals to the trailer microprocessor to execute the same code and signals as the master and shadow microprocessors a known number of cycles behind. The outputs of the master and shadow microprocessors are compared and the trailer microprocessor is halted, along with the master and shadow, when a "mismatch" occurs between the outputs of the master and shadow processors. When the internal states of all three processors are scanned, the differences in the internal state of the shadow processor before and at a failure can be theoretically compared. The trailer microprocessor may be stepped cycle-by-cycle up to and past the point of failure of the shadow processor for further analysis.

Abstract: In a computer controlled graphics system, processes are provided for detecting errors incurred in a display list having variable length instruction/parameter (I/P) sets, the errors occurring during parameterization, transmission, branching, and storage of the display list. Each process includes generating a display list including I/P sets, each I/P set including n parameter words following an instruction word. In each embodiment, a display list is encoded, transmitted, stored in a memory unit, and verified. In one embodiment, the display list is encoded by storing into each instruction word of each I/P set a parity bit of a value representative of the parity of the whole I/P set. In another embodiment, the display list is encoded by storing within each instruction word of each I/P set an m-bit checksum value. The m-bit checksum value is generated by partitioning each I/P set into y m-bit partitions which are summed, ignoring overflow.

Abstract: A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.

Abstract: A computer system such as a debugging system for a microcomputer system includes a display unit and a supervisor for receiving at least one of the plurality of status data from the microcomputer system independently from the execution of a program in the microcomputer system and displaying the read status data on the display unit. The microcomputer system includes the plurality of peripheral circuits respectively having status flags, each of which stores the status data of the corresponding peripheral circuit, and a CPU executing the program. The status data are updated as the execution of the program and the CPU can read the status data of each of the status flags. An emulation control circuit generates a status clock signal independently from the execution of the program by the CPU and a selector sequentially and repeatedly selects one of the plurality of status data in response to the status clock signal to output the selected status data to the supervisor.

Abstract: A disaster recovery system providing remote data shadowing between a primary and a secondary site uses a method and apparatus for swapping, or switching, host directed I/O operations from a primary data storage device to a secondary data storage device in a remote copy duplex pair. Application programs running in a host processor at the primary site first quiesce all I/O operations and record updates targeted to the primary data storage device. The remote copy duplex pair is checked to verify that the secondary data storage device is a fully synchronized copy of the primary data storage device.

Abstract: A computer-based system is provided for preventing unauthorized duplication of a particular software program among a plurality of active software programs executed on a computer. The system receives an indication that the computer is executing the particular software program, and then monitors operation of the computer to determine which of the plurality of the active software programs is being currently executed. When the system determines through the monitoring that the particular software program is not the currently executed software program, it disables execution of the particular software program.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory subsystem. A checkpoint memory element, which may include one or more buffer memories and a shadow memory, is also appended to this main memory subsystem. During normal processing, an image of data written to primary memory is captured by the checkpoint memory element. When a new checkpoint is desired, thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault, the data previously captured is used to establish that checkpoint. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

Abstract: A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.

Abstract: Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access.

Abstract: A method and system for converting an email message to a facsimile only for authorized users of an account which has been previously created. After a user registers and provides an email address and appropriate billing information, stamps or authorization codes are transmitted to the user via email. When the user desires to have an email message transmitted via facsimile to another party, the user transmits, from a registered account, an email message which includes the fax number to which the facsimile is to be transmitted and contains a stamp. A computer operated by a service provider receives the email message, checks to see that the email message originated from a valid account, and contains a valid stamp. The stamp is then removed from the email, the email is converted to an image which is transmitted via facsimile to the appropriate telephone number, and the account which was previously registered is billed.

Abstract: A system that automatically detects logical errors when compiling a program. The system detects such logical errors as a signal handler routine modifying the errno global variable, a signal handler routine calling a non-reentrant library function, a signal handler routine calling a non-reentrant user function, and a signal handler routine calling a memory allocation function without first disabling all other signal handlers. The system also detects using "/n" at the end of a string.

Abstract: A method for accessing data on a fieldbus device in a fieldbus network which comprises user selectable models of data ownership. The fieldbus device includes a user application executing on the fieldbus device and a function block shell executing on the fieldbus device. The method comprises receiving a request to access data on a fieldbus device. In response to the request, the function block shell determines the ownership attribute of the data, wherein possible ownership attributes include user owned or shell owned. The shell accesses the data in response to determining that the ownership attribute of the data is shell owned. The user application accesses the data in response to determining that the ownership attribute of the data is user owned. The method further includes shell notify and user pointer ownership models which provide additional flexibility.