Abstract: In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters store performance data generated by each processor while executing the instructions. An interrupt handler executes on each processors, the interrupt handler samples the performance data of the processor in response to interrupts. A first memory includes a hash table associated with each interrupt handler, the hash table stores the performance data sampled by the interrupt handler executing on the processor. A second memory includes an overflow buffer, the overflow buffer stores the performance data while portions of the hash tables are active or full. A third memory includes a user buffer, and means are provided for periodically flushing the performance data from the hash tables and the overflow to the user buffer.

Abstract: A system (10) is provided for analyzing failures arising in computing environments. The system (10) includes an interface (12) which receives information relating to a current failure in a computing environment. A database (18) stores information relating to at least one prior failure in the same computing environment or another computing environment. A processor (22), which is coupled to the interface (12) and the database (18), compares the received information relating to the current failure with the stored information relating to the prior failure in order to find similarities. The processor (22) may then instruct a user to take appropriate action in response to similarities between the current failure and the prior failure, thereby analyzing the failures.

Abstract: A mechanism for maintaining a consistent state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory via a memory bus. A shadow memory element, which includes a buffer memory and a main storage element, is also attached to this memory bus. During normal processing, data written to primary memory is also captured by the buffer memory of the shadow memory element. When a checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured in the buffer memory is then copied to the main storage element of the shadow memory element. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

Abstract: A method and system for providing secured access to a server connected to a private computer network protected by a router acting as a firewall is provided. The method includes establishing a bypass communication route around the firewall router, exchanging information between a client and the server via the bypass communication route, and closing the bypass communication route. The system includes an external machine, an external communication channel, an internal machine, an internal communication channel, and a dedicated private communication channel. Each of these components in combination form a bypass communication route around the firewall router.

Abstract: A method for rebuilding contents of a malfunctioned direct access storage device within a log-structured array is disclosed. In accordance with the method and system of the present invention, each direct access storage device within a log-structured array is divided into multiple segment-columns, and each corresponding segment-column from each direct access storage device within the log-structured array forms a segment. A segment is first located within the direct access storage devices. A determination is made as to whether or not the segment is empty. In response to a determination that the segment is empty, a pointer is moved within a segment-column mapping table from pointing to a segment-column in the malfunctioned direct access storage device to point to a segment-column in a spare direct access storage device of the segment.

Abstract: In order to make it possible to simultaneously test 16 semiconductor memory ICs each having 16 I/O ports, a connecting part acting as an adapter is inserted between each of the semiconductor memory IC and a memory IC tester part. In testing a semiconductor memory IC, first, common write data for testing is simultaneously written to a large number of memory cells of the IC. For this purpose, write data from a write data generator in the memory IC tester port is written to the memory cells through an input and output change-over circuit, a write data branching circuit, and the I/O ports. Thereafter, data is read from the memory cells and supplied to an EX-OR circuit from the 16 I/O ports. The EX-OR output is supplied to an operational result data comparison and inspection unit of the memory IC tester part via the input and output change-over circuit. The value of the EX-OR output goes to a high level only when all of the read data from the 16 I/O ports are equal, and goes to a low level otherwise.