Abstract: An automatically configurable storage subsystem for use in conjunction with a computer system. The storage subsystem includes a storage controller attached to the computer system and multiple data storage devices which are configurable in multiple diverse arrays. A data transfer parameter is specified by a user which preferably sets forth an estimated average size of a future data transfer and/or an estimated percentage of future sequential data transfers. The data transfer parameter(s) is then coupled to the storage controller and is utilized to automatically configure at least certain of the multiple data storage devices into an appropriate array for future data transfers.

Abstract: A method and system for heterogeneous network testing by a plurality of users is disclosed. The present invention provides at least one client machine, an execution server, and at least one custom server in a LAN (local area network) or WAN (wide area network) environment for heterogeneous network testing in which one or more client machines may communicate with the execution server which in turn manages one or more custom servers that execute requested test cases. The Custom Servers may be of various types, including ISDN servers, SS7 servers and CG servers. A user on the network communicates to a Client Machine which test case or test cases are to be executed. The requested test cases are retrieved and may be edited by the user on the Client Machine prior to communicating the test case information from the Client Machine to the Execution Server which coordinates the execution of test cases by an appropriate Custom Server.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A device for executing a main program written in an interpreter language includes a processing unit for executing a program written in the interpreter language and a monitor program which is written in the interpreter language for monitoring the execution of the main program. The device further includes a first switching unit for switching the processing unit from executing the main program to executing the monitor program after an execution of one execution unit of the main program, and a second switching unit for switching the processing unit from executing the monitor program to executing the main program after an execution of the monitor program.

Abstract: A method and system for recovering after a crash of an instance in a database is disclosed. According to the method, transaction information corresponding to all the transactions that existed in the failed instance is inspected. These transactions that were active at the time the instance crashed are marked as "dead." The database is made available to users after updating the transaction information and before undoing all of the changes or updates performed by dead transactions. The changes made by the dead transactions may be undone by new transactions on a on-demand basis after the database is made available. Specifically, when a new transaction is waiting to obtain a lock on a resource held by another transaction, the new transaction determines whether the owner of the lock is one of the dead transactions. If so, the new transaction rolls back some or all of the changes made by the dead transaction.

Abstract: A method is described for ordering a plurality of messages from a plurality of sources wherein, in order for all the application processes to receive the messages in the same order, a single relay process common to all the sources is selected from the application processes, the other application processes constituting slave processes. All messages broadcast by the sources are rebroadcast from the relay process to all the application processes, including the relay process. The relay process processes data from all messages that it rebroadcasts. The slave process processes only data from messages received via the relay process, data from messages received directly from the sources not being processed. Applications include data processing systems, in particular where part of the software is replicated.

Abstract: Errors or failures in a transmission system (10) can be accurately predicted by a system (18) which processes error or failure data collected by the transmission system during uniform intervals to yield data indicative of the errors or failures during each of a plurality of non-uniform, overlapping intervals. The errors or failures measured during the non-uniform intervals are selectively weighted and summed within a neural network (22), trained with historical error or failure data, to yield a set of predictions, each representing the predicted number of errors or failures during each non-uniform interval. The predictions from the neural network (22) are then thresholded by a control unit (24) and used to raise an alarm which signals the possibility of error or failure in the transmission system.

Abstract: A data input circuit is used in a memory device having an externally accessible data pin. The data input circuit includes first and second data output terminals and a test terminal that receives a test signal. A data converter is coupled to the first and second data output terminals and to the test terminal, and places complementary signal levels on the first and second data output terminals when the test signal is absent from the test terminal, and places a same signal level on both the first and second data output terminals when the test signal is present on the test terminal. The data input circuit may include an input terminal that is coupled to the data pin, where the data converter is coupled to the input terminal.

Abstract: A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: An apparatus and method for unilaterally-controlled, time-insensitive recovery of disconnected data links provides for user-transparent recovery, without requiring inputs from a user or other intervention. Data and executable operations may be preserved, as re-booting is not required. Optionally, opportunity for user intervention may be provided, at a user's request. Recovery may occur automatically by use of expert knowledge applied to reported system errors from the disconnected communication link. An apparatus may rely on a logical device within an actuator or machine of mechanical, pneumatic, hydraulic, electrical or electronic character. A task to be reported to an actuator as successful or failed, may be internal to the actuator, internal to the logical device, or external to both. Data structures stored in a memory device, may implement the invention readily from within an application running on a processor in a computer.

Abstract: An intelligent status monitoring, reporting and control module is coupled to a SCSI bus that interconnects a cluster of SCSI-compatible data storage modules (e.g., magnetic disk drives). The status monitoring, reporting and control module is otherwise coupled to the cluster of SCSI-compatible data storage modules and to power maintenance and/or other maintenance subsystems of the cluster for monitoring and controlling states of the data storage modules and power maintenance and/or other maintenance subsystems that are not readily monitored or controlled directly by way of the SCSI bus. The status monitoring, reporting and control module sends status reports to a local or remote system supervisor and executes control commands supplied by the local or remote system supervisor. The status reports include reports about system temperature and power conditions. The executable commands include commands for regulating system temperature and power conditions.

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO.

Abstract: Apparatus to provide security for a keypad processor of a transaction terminal includes a secured processor coupled to a keypad and processor of the transaction terminal. The apparatus may operate in a secured or an unsecured mode. In a secured mode, the apparatus prevents the fraudulent acquisition of information, such as personal identification numbers (PIN), entered through the keypad. By encrypting data entered through the keypad, the apparatus prevents the fraudulent acquisition of information transmitted to a processor such as a central computer of a bank. The secured processor provides actual and false sampling of the keypad and simulates keypad data entries to prevent an electronic eavesdropper from determining the actual keypad entries.

Abstract: In a connection-oriented network, a source network node responds to a connection request from a source user by sending signaling messages to adjacent nodes to request reservation of multiple paths by specifying a QOS parameter of minimum level and then establishes to a destination node if the requests are accepted. The source network node selects one of the established paths and sends a second signaling message to the node of the selected path, requesting that the QOS parameter of the selected path be increased from the minimum level to a level specified by the connection request, and establishes a connection from the source user to a destination user via the selected path if the second signaling message is accepted by the node of the selected path.

Abstract: An improved recovery method utilizes sequence numbers to order log records and reduce the excess compensating actions due to a failure during recovery. Next undo records are written to the log after a preset number of compensating actions which include the sequence number of the record currently being scanned. After a failure, all records between the next undo record and the record having the sequence number included in the next undo record are ignored during when the log is scanned backwards.

Abstract: A computer implemented method and apparatus for mounting a user removable media in a computer system includes acquiring a media identifier input and a function identifier input from a user of the computer system. The media identifier input identifies the user removable media, and the function identifier input specifies a mounting operation to be performed on the user removable media. The media identifier and the function identifier inputs are processed to access a system media interface of the computer system, for example, by converting the media identifier input to a physical path of the user removable media in the computer system, and determining if the physical path of the media identifier input is valid within the computer system. A simulated media event is generated to mount the user removable media in the computer system. If desired, a determination may be made whether the user has valid permission to control the user removable media identified by the media identifier input.

Abstract: An apparatus in a display system for setting an ID password includes a microprocessor, an input device and an output device. The input device incorporates an array of user manipulated keys so as to allow a user to input an ID code to the microprocessor. The microprocessor includes a program for comparing an inputted ID code with preset ID data stored in a memory to determine consistency therebetween. The microprocessor further includes a program for displaying information visually to a user and so as to allow only an authorized user to use the display thereby protecting private confidential information from misuse. A method for implementing the ID password system includes generally the steps of inputting an ID code via an input device, comparing an inputted ID code with a preset data stored in a memory and thereby controlling the display. As a result, a display employing an embodiment of the present invention may be used by an authorized user only.

Abstract: A failure reporting system which includes a plurality of reporting tools for reporting detected failures in a system to be observed is provided. The reporting tools include at least two tools from the group consisting of an audio reporting tool, a visual reporting tool and a text reporting tool. The audio reporting tool includes at lest one microphone, the visual reporting tool includes at lest one video camera and the text reporting tool includes at least one keyboard. The system also includes a control system for activating a selected number from the plurality of reporting tools at a time and an audio recognition unit for discriminating between audible reports and other audible information.

Abstract: A disk array stores data records and parity records. The data records are transferred to the disk array through a control unit that is connected to a host processor. The disk array is part of a disk unit having a processor for generating parity records from information sent by the control unit to the disk unit. The parity record is generated and stored in the disk unit to reduce the number of data transfer operations between the control unit and the disk unit for storage systems using disk array disk units.