Abstract: A semiconductor chip is provided with a function selection circuit for selecting memory functions according to the information stored in nonvolatile memory elements is sealed in a package, and the memory functions are set finally by writing the nonvolatile memory element in that state or in a state in which the semiconductor chip is mounted on a board. By setting the type of a semiconductor memory according to the above procedure, the process from the wafer process up to the assembling step can be made common, and hence the mass-productibity and the production control can be facilitated. Semiconductor memories having memory functions conforming to user specifications can be provided in a short time.

Abstract: In a serial access memory device in which dynamic memory cells and serial registers are combined, the chip area occupied by the added serial registers can be reduced and thereby the cost of the memory chip can be reduced. The dynamic serial registers (SR) for reading data in series are provided in correspondence to the dynamic cell array (CA). When data are read under control of a transfer gate control block (X'fer CTL), the address is stored in an address compare block (X'fer Add). During the refresh of the cell array (CA) by a refresh control block (Ref CTL), the address of the cells being refreshed is given to the address compare block (X'fer Add). When both address match, the data of the cell array (CA) are transferred again to the serial registers (SR) through the transfer gate control block (X'fer CTL) to refresh the data of the serial registers.

Abstract: A Low-voltage Electrically Erasable, Electrically Programmable Read Only Memory (EEPROM) and a method for reading memory cells in the EEPROM. During a read operation address input is provided to an address latch and edge detector, which supplies a changed address signal to a charge-sharing word line voltage generator, supplies word line address signals to a word line address decoder, and supplies bit line address signals to a bit line address decoder and sense amplifier circuit. The word line address decoder provides a positive voltage from a positive voltage source to a selected word line in the memory array and provides a voltage that is negative with respect to ground to deselected word lines. The bit line address decoder and sense amplifier circuit grounds selected source bit lines and senses drain to source current to read the memory cells.

Abstract: When a current flows through a selected memory cell transistor at the time of data reading, the gate voltage of an n-channel MOS transistor, which makes up the current flowing through the load, rises. Thus, when a current flows through a selected memory cell transistor at the time of data reading, the current through the load is increased so that the time required for data reading when the current flows through the selected memory cell transistor can be shortened and the data reading can be effected at a high speed.

Abstract: Memory (120) in a device (100) that includes a power source (105) is erased when an alarm triggering event is detected. An alarm signal is provided that is used to determine whether the memory (120) has been erased since a transition from normal to low power mode. It is only when the memory (120) has not been erased since such a transition, that the memory (120) is erased, thereby providing an energy efficient erasure process.

Abstract: A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The second transistorless device may be a diode or a resistor. The read/write operation of the transistorless memory cell is performed in a current mode.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: A video RAM capable of minimizing the peak current generated during a data transfer operation performed between a RAM and a SAM, and a method for suppressing the peak current in a SAM block. The video RAM comprises a first power source, a second power source, unit latch circuit which inputs the first and second power sources as a source power, a SAM block composed of a plurality of unit latch circuits, and peak current suppression means formed on a path through which the first and second power sources are inputted to the unit latch circuit.

Abstract: Disclosed herein is a semiconductor memory device comprising an N-channel transistor and a P-channel transistor Q33 which are provided in parallel between a sense node and a power supply line, The N-channel transistor has a threshold value of near 0 V and a specified current drive capability. The P-channel transistor Q33 charges the sense node up to the level that is smaller than a power supply voltage by a threshold value thereof and the level at the sense node is then changed by use of the N-channel transistor in accordance with data stored in the memory cell coupled to the sense node.

Abstract: Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines.

Abstract: A circuit which responds to an external standby command (a transition in a chip enable signal from an external device) by generating a delayed internal standby signal. The internal standby signal functions by switching selected components of the circuit (such as address buffers) from an active mode to a standby mode. In preferred embodiments, the circuit is a memory circuit implemented as an integrated circuit. The amount of the delay in generating the delayed internal standby signal is selected to achieve a desired decreased average response time to a sequence of commands (such as memory access commands) without excessive power consumption. In embodiments in which the circuit is a memory chip (such as a flash memory chip) having address access time in the range from 60 ns to 80 ns, the delay typically is from about 100 ns to about 200 ns.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate with a first conductivity type, a first well of a second conductivity type formed on the semiconductor substrate, a second well of the first conductivity type formed on the first well, a plurality of memory cells provided in the second well and each including a tunneling insulation film having a thickness allowing a tunneling of carriers, a floating gate electrode provided on the tunneling insulation film, an interlayer insulation film provided on the floating gate electrode, a control electrode provided on the interlayer insulation film, and a pair of diffusion regions of the first conductivity type formed on the second well at both sides of a channel region.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A semiconductor memory device includes at least one word line, at least one memory cell coupled to the word line, a decoder circuit responding to address information to generate a word line drive signal taking one of an active level and an inactive level, a signal generator generating a reset signal tacking an active level in a reset mode and an inactive level in a selection mode, and a word line driver coupled to receive the word line drive signal and the reset signal and to the word line. The word line driver includes a first drive circuit responding to the active level of the reset signal to drive the word line to a non-selection level and maintaining the word line at the non-selection level when the word line drive signal and the reset signal are at the inactive level. A second drive circuit responds to the active level of the word line drive signal and the inactive level of the reset signal to drive the word line to a selection level.

Abstract: In a semiconductor memory device, amplification of data is realized with a high speed without influences of fluctuations at fabrication. Potentials of a common data line pair are set at a reference voltage by current negative feedback of differential amplifiers. In this way signal amplitude in the common data line pair is decreased. A current from a memory cell is transformed into a voltage by transistors in a negative feedback loop. Even if there are fluctuations or an offset voltage in the differential amplifiers, it is possible to decrease the signal amplitude in the common data line pair and to realize a high speed data amplification with low electric power consumption.

Abstract: A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder.

Abstract: A memory device includes a plurality of memory arrays each having a plurality of memory cells arranged in rows and columns, and at least one spare arrays having the same arrangement of memory cells as the memory array. A word line connecting a row of memory cells at a first address in a memory array is replaced by a spare word line connecting a row of memory cells at the first address in the spare memory array. Such a replacement scheme provides a word line by word line replacement and an array by array replacement with a simplified replacement control circuit and reduced area penalty.

Abstract: Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.