Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors.

Abstract: There are provided a plurality of ferroelectric capacitors each of which having one of a pair of electrodes thereof connected with one terminal of a switch element which has the control terminal thereof connected with a first address selecting line. Second address selecting lines are respectively connected with the other electrodes of the ferroelectric capacitors to construct a unit memory circuit. When the switch element is turned ON by the first address selecting line, one of the second address selecting lines is brought into a selecting state to feed such a voltage as to polarize the ferroelectric capacitors. The remaining address selecting lines are set to an unselect potential so that the voltage to be applied to the unselected ferroelectric capacitors coupled to the remaining address selecting lines may be about one half as high as that applied to the selected ferroelectric capacitor.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: A memory includes a first ferroelectric capacitor and a second ferroelectric capacitor electrically connected in a parallel arrangement, and writing circuitry that writes controllably different polarization states into the two ferroelectric capacitors using a single input signal. Read circuitry senses the difference in stored polarizations in the first ferroelectric capacitor and the second ferroelectric capacitor. This sensing circuit causes only a partial switching of the polarization state of the first ferroelectric capacitor and does not disturb the polarization state of the second ferroelectric capacitor. There is a restoration circuit to restore the original ferroelectric polarization of the ferroelectric capacitors following reading.

Abstract: A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump.

Abstract: A semiconductor memory device as a video memory is disclosed. The video memory includes a first memory cell array plate having a plurality of first pairs of digit lines and a plurality of second pairs of digit lines, a plurality of first sense amplifiers arranged along one side of the first array plate and provided for the first pairs of digit lines, a plurality of second sense amplifiers arranged along an opposite side of the first array plate and provided for the second pairs of digit lines, a second memory cell array plate having a plurality of third pairs of digit lines, and a plurality of third sense amplifier provided for the third pairs of digit lines. A plurality of pairs of dummy digit lines are further provided in the second memory cell array plate so that the first and second cell array plates has the pairs of digit lines equal in number to each other.

Abstract: A circuit for regulating floating gate injection voltage comprises a volt regulator electrically coupled to a floating gate device. The floating gate device includes an electrically conductive floating gate capacitively coupled to a programming terminal by an injection capacitance and to a bias terminal by a bias capacitance. The voltage regulator establishes a substantially constant rate of charge onto the floating gate when a programming voltage is applied to the floating gate device and the voltage regulator.

Abstract: A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals.

Abstract: The present invention provides a semiconductor memory circuit which can restrict the increase of an operation current in a flash write mode to a minimum even when there are problems caused in the manufacturing process such as short-circuits in the wiring. A timing control circuit of the semiconductor memory circuit of the present invention comprises an FW latch signal generation circuit and a latch circuit both for detecting that a row address strobe signal, an RAS signal and a flash write enable signal inputted have become active, and an FW gate signal generation circuit for activating the FW gate signal for only a limited fixed time determined by a delay circuit when an FW gate activation signal is outputted from the latch circuit which has detected the activation of both signals. With the FW gate signal activated, the flash write gate switch turns active for performing the flash write activity.

Abstract: A method for operating a Flash memory having a plurality of memory blocks. In a first method, data is written to a memory block having less than the predetermined threshold of memory remaining. Any remaining data is written to a memory block having the largest amount of memory remaining. In a second method, data is written to a memory block having a least amount of memory remaining when an average of the memory used in each block falls below the predetermined threshold. Any remaining data is also written to a memory block having the largest amount of memory remaining. A block erase is performed on a memory block by first copying any data to be saved to a copy block of the Flash memory. Each memory block has an identifying code. An identifying code of the copy block is changed to an identifying code of the memory block. A block erase is then performed on the memory block and the identifying code of the memory block is changed to the identifying code of the copy block.

Abstract: A static random access memory comprises word lines for receiving a cell selection signal, and arrays of first memory cells connected to the word lines. First load circuits are respectively connected to the arrays of the first memory cells for supplying a voltage from a voltage source to the arrays. First amplifier circuits are connected respectively to the first memory cells. A second, or dummy memory cell identical to each of the first memory cells is provided for storing a predetermined binary digit. A second load circuit identical to each of the first load circuits supplies the voltage from the voltage source to the dummy memory cell. A second amplifier circuit identical to each of the first amplifier circuits is connected to the dummy memory cell.

Abstract: A non-volatile semiconductor memory device comprises a plurality of semiconductor layers of a first conductivity type, extending parallelly in a column direction and isolated from each other; a plurality of memory cells disposed in a matrix of columns and rows, each having source and drain regions of a second conductivity type, a channel region between the source and drain regions and a gate structure formed on the channel region with a gate insulating layer interposed therebetween and including a floating gate, an interlayer insulating layer, and a control gate. The memory cells are divided into a plurality of groups formed on the semiconductor layers, respectively, so that all the memory cell groups are formed on one of the semiconductor layers and the drain-source circuits of the memory cells of each group are connected to form a series electrical path.

Abstract: A ROM includes an address transition detection circuit and a supply voltage rising detection circuit. The supply voltage rising detection circuit inhibits an operation of the address transition detection circuit until a supply voltage reaches a predetermined voltage after application of power.

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

Abstract: An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

Abstract: The memory cells connected to the word lines in the odd-numbered rows differ from the memory cells connected to the word lines in the even-numbered rows in characteristics. A dummy cell DMC1 has the same characteristics as those of the memory cells connected to the word lines in the odd-numbered rows, and a dummy cell DMC2 has the same characteristics as those of the memory cells connected to the word lines in the even-numbered rows. Because the dummy cell DMC1 is selected together with a word line in an odd-numbered row, and the dummy cell DMC2 is selected together with a word line in an even-numbered row, a suitable reference potential can be supplied in accordance with the selected memory cell. A sense amplifier compares the potential on the bit line to which the selected memory cell is connected with the potential supplied from the selected dummy cell. Therefore, the sense amplifier can sense the potential at the selected memory cell accurately.

Abstract: A DC--DC converter using a planar inductor is arranged in an IC memory card incorporating an EEPROM memory chip, and power supply is performed such that a voltage is adjusted by a dropping regulator, thereby reducing power consumption. The power consumption of the IC memory card incorporating the EEPROM can be reduced. The IC card can be driven by a single power supply, thereby providing a compact portable information device which can be driven by a battery for a long time.

Abstract: An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.

Abstract: A device is provided for detecting the content of cells of a memory, and for minimizing the read access time of a high-capacity EPROM memory in which cells are organized as a set of bit rows. A comparator including a differential amplifier compares a reference current from a reference column with a read current invoked in a cell of a bit row. The reference current and a read current flow through a resistive reference element and a resistive read element respectively. These resistive elements are connected, at one end, to a supply voltage source and, at the other end, to the non-inverting input and the inverting input respectively of the differential amplifier. The differential amplifier delivers as output a detection signal. In a preloading period the output of the differential amplifier is connected to its inverting input.

Abstract: The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal.