Abstract: The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

Abstract: A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

Abstract: A ferroelectric memory having a structure in which source and drain are formed on a semiconductor substrate, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a ferroelectric gate transistor memory cell having a ferroelectric gate transistor structure including a gate electrode made of a conductive gate electrode, is arranged on the thin film. An X selection line (column) is connected to the gate of the memory cell, and a Y selection line (row line) is connected to the source and drain, or the column and row of the X and Y selection line are connected to the memory cell vice versa. The memory can be driven only by 1-transistor/1-cell without a pass gate transistor, and the data can be non-destructively read out by applying a voltage lower than the coercive voltage of the ferroelectric to the gate electrode, the source and drain.

Abstract: A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14.

Abstract: An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.

Abstract: A redundancy enable circuit of a semiconductor memory device, including an address input unit provided with a plurality of repair fuses and a plurality of pass transistors for respectively receiving address signals necessary and unnecessary for a refresh option, the address input unit allowing the necessary ones of the of the address signals to be inputted respectively at corresponding ones of the pass transistors and thereby to control the signal-received pass transistors while preventing the unnecessary ones of the address signals from being inputted respectively at corresponding ones of the pass transistors, whereby an increased repair efficiency is obtained.

Abstract: N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

Abstract: A semiconductor memory array having a plurality of rows of memory cells, a word line, which extends into at least two memory blocks, to carry drive signals, such as read select and deselect signals, erase select and deselect signals, and program select and deselect signals for selective delivery to a subword line. Two pairs of subword lines and associated drivers are arranged with each pair selectively connectible to a portion of the word line within the block containing the subword line pair and to an associated set of memory cells. Each subword line driver selectively delivers drive signals from the word line to a respective, selected one of the subword lines. The subword lines and their drivers are arranged to extend from opposite sides into the block with which the subword line pairs are associated to reduce the layout size necessary, and to enable fewer word line drivers to be needed for a particular layout pitch.

Abstract: A semiconductor memory device includes a sense amplifier which senses data read out from a memory cell, a transfer gate coupled to an output of the sense amplifier, and a data latch circuit coupled to the transfer gate. The data latch circuit includes two MOS transistors of a same conductivity type connected in series between a pair of I/O data lines. The gates of the two MOS transistors are cross-coupled to the data lines respectively, thereby enabling a rapid data transfer between the memory cell and a data bus.

Abstract: The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An electric circuit of the present invention has one-hundred-twenty pins along the length of the housing. The housing of the memory device has a length of approximately 85.6 mm and a width of approximately 54.0 mm. The left and right side socket interface portions of the housing have a minimum width of approximately 3.3 mm. The top socket interface portion has a maximum thickness of approximately 3.5 mm and a minimum height of approximately 3.0 mm. The bottom socket interface portion has a maximum thickness of approximately 5.0 mm and a minimum height of approximately 10.5 mm. Furthermore, the memory device interface portion of the present invention includes at least one pin which provides access to an address signal which indicates a memory array address location within the memory device.

Abstract: A semiconductor memory, particularly a sychronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level to a predetermined level after the write operation has completed.

Abstract: The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per output. Each of the plurality of outputs is connected to one of a plurality of memory cells. Each memory cell comprises an impedance element, its impedance value representative of the data value stored therein. All of the memory cells are thereafter connected to a sum line and a read out circuit. When the signal source provides one of the sequence signals to one of the memory cell impedance elements, it affects the signal on the sum line in a manner that is related to the impedance value of the memory cell. By applying each signal in the sequence to a different impedance element, the voltage on the sum line is directly affected by each of the impedance elements in sequence.

Abstract: A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.

Abstract: A clock driver is mounted in the center of a printed-circuit board, and a plurality of synchronous DRAMs are arranged on left and right hand sides of the clock driver in different banks. A clock signal is supplied from the clock driver to the synchronous DRAMs via clock wires. Wiring distances for supplying the clock pulse from the clock driver to a pair of synchronous DRAMs included in the different banks are determined to nearly equal to prevent a time difference of a timing signal in a data recording and reproducing operations of the respective banks and to solve a skew mismatching.

Abstract: An integrated circuit (106) having an optically erasable portion (114) is joined to a substrate (102) such that the optically erasable portion faces the substrate. The substrate (102) includes an aperture (104) that exposes the optically erasable portion (114) of the integrated circuit providing erasing capability to the integrated circuit (106). A plug (110) impermeable to light may be inserted into the aperture (104) to provide a sealed window to the optically erasable portion (114) of the integrated circuit (106).

Abstract: An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address signals to generate a redundancy selection signal for the selection of an associated redundancy memory element when the address signals coincide with the address stored therein, and combinatorial circuit means supplying the non-volatile memory registers with an inhibition signal for inhibiting the generation of the respective redundancy selection signals when the address signals coincide with the address stored in a non-programmed non-volatile memory register; the integrated circuitry comprises multiplexing circuit means, controlled by a control signal generated by a control circuitry of the memory device, for transmitting the redundancy selection signals to output pads of the memory device when the control signal is activated;

Abstract: A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors.

Abstract: An arrangement for controlling the application of erase biasing voltages to the memory devices of a flash EEPROM memory array which arrangement precludes application of any erase biasing voltage until all of the devices are tested to determine which if any devices are programmed, and then allows application of erase bias voltages only to those blocks of the memory array which include devices which are programmed. In one embodiment, a power-on state machine which is used to read the state of the devices to initialize the array is used to test the condition of the array whenever an erase is desired and latching means are used with each block to preclude any erasing until it is determined that the block, in fact, includes programmed devices.

Abstract: A memory control circuit for controlling a memory chip enable signal without unnecessary power consumption in a non-volatile memory chip during the backup state. When a backup signal (BUP) shows that the card is in a backup state, all of the memory chip enable signal output lines are set to a high-impedance state by controlling a backup time control means inserted therein, and pull-up resistors 20 are connected to the memory chip enable signal output lines 8 connected to the volatile memory chip 2 for setting them to a "H" level, and an A power source 5 without backup is connected to the memory chip enable signal output lines 8 connected to the non-volatile memory chip 3 through a pull-up resistor 30, thereby preventing unnecessary current from flowing.

Abstract: A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.