Abstract: To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a node (source or drain) of the transistor. A reference voltage is asserted to a second input terminal of the differential amplifier. A load provides a current which charges the node, and the differential amplifier adjusts the gate voltage of the memory cell to an equilibrium value where current through the transistor is equal to current through the reference cell. The equilibrium value of the gate voltage depends on and indicates the threshold voltage of the transistor. In one embodiment of the invention, the load is a current source which mirrors a current through a reference cell that is structurally identical to the transistor, and the drain of the reference cell provides the reference voltage to the amplifier.

Abstract: A first interconnection frame is provided on a semiconductor substrate so as to surround a central circuit strip. A second interconnection frame is provided on first metal interconnection frame with an insulating film therebetween. Both ends of a supply line are in contact with second interconnection frame. There is a gap provided between both ends of a ground line and second interconnection frame. Ground line and first interconnection frame are connected, using a via hole provided in the insulating film. Thus, an improved dynamic random access memory in which the voltage levels of supply lines and ground lines are stabilized is provided.

Abstract: A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of the nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.

Abstract: A multi-layer magnetic memory cell is provided, with magnetic end vectors adjacent the ends of the cell pinned in a fixed direction. To pin the magnetic end vectors, a magnetic field is applied to an end of at least one of the layers of magnetic material in the cell to move the magnetic end vectors in the magnetic material at the end of the cell into a fixed direction. Pinning material is then disposed adjacent to the end to maintain the magnetic end vectors in the magnetic material at the end of the cell in the fixed direction.

Abstract: The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuits. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

Abstract: A non-volatile semiconductor memory which is capable of high speed and highly accurate analog data writing. The memory includes a first MOS type transistor having a first floating gate which is electrically isolated. A first electrode is capacitively coupled with the first floating gate. A second electrode is connected via a tunnel junction with the first floating gate. A third electrode is capacitively coupled with the second electrode. A second MOS type transistor interconnects the first and second electrodes. A means is provided for applying a predetermined potential difference between the first and third electrodes to thereby cause a tunnel current to flow in the tunnel junction and to store an electric charge in the first floating gate to thereby cause the second MOS type transistor to conduct when the electric charge has reached a predetermined value.

Abstract: A semiconductor memory is disclosed having a primary memory array (12) and a dummy column (14) associated therewith that is comprised of a plurality of dummy memory cells (70). The dummy memory cells have a predetermined value stored therein and are sensed with a dummy sense amplifier (18). The dummy sense amplifier (18) has a predetermined offset disposed therein, such that it is in a predetermined state prior to the bit lines separating a sufficient amount to detect the logic state in the dummy memory cell, with an offset disposed therein. This offset prevents the state of the dummy sense amp from being changed until the bit lines are separated by a predetermined value. The primary sense amplifiers associated with the primary memory array (12) are not enabled until the dummy sense amplifier has detected the dummy bit lines as being separating by the predetermined amount.

Abstract: A semiconductor device constituted by a booster circuit, memory cell arrays, a sense amplifier circuit, transmission gate circuits, equalizing circuits and a control circuit applying a boosted potential respectively to the gates of MOS transistors of the transmission gate circuits and the equalizing circuits when no memory cells of the memory cell arrays are selected whereby the capacitance of de-coupling capacitors connected to output terminals of the booster circuit can be reduced thereby contributing to reduction in chip area.

Abstract: Apparatus is disclosed for disabling the charge pumps in an integrated circuit memory when data is being read from the memory.

Abstract: A semiconductor memory has a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a power source unit, and a plurality of sense amplifiers. The memory cells are formed at intersection portions of the bit lines and the word lines, and each of the memory cells includes a transistor and a capacitor. The power source unit is connected to the capacitors of the memory cells. Each of the sense amplifiers, which is connected to a corresponding one of the bit lines and the power source, is used to amplify a voltage between a potential of the corresponding bit line. This memory realizes high integration, large capacity, and low power consumption.

Abstract: A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry.

Abstract: New types of memory cell structures (20, 40) for a magnetic random access memory are provided. A memory cell (20, 40) has a plurality of cell pieces (21-24) where digital information is stored. Each cell piece is formed by magnetic layers (27, 28) separated by a conductor layer (29). A word line (25, 41) is placed adjacent each cell piece for winding around cell pieces (21-24) and meandering on a same plane on cell pieces (21-24), for example. The invention attains less power consumption and effective usage for a word current.

Abstract: A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

Abstract: A method and a circuit of reducing cell plate noise induced by memory access are provided. The circuit includes a sample and hold circuit, a differential amplifier and a current source. The sample and hold circuit maintains a sample voltage identical to the normal level of the reference cell plate voltage. The differential amplifier compares the sample voltage with the reference cell plate voltage during memory access in the DRAM and generates a difference voltage corresponding to the cell plate noise. The current source, which is controlled by the difference voltage, can modify the reference cell plate voltage to reduce the cell plate noise during memory access.

Abstract: A memory cell is constructed using a ferroelectric capacitor having an insulator formed of a ferroelectric material that has a zero field capacitance which is controllably dependent upon the electrical charging path by which the zero field capacitance is reached. Preferably, the material is characterized by a first zero field capacitance following saturation of the polarization by a first applied voltage applied in a first polarization direction, and a second zero field capacitance following saturation of the polarization by the first applied voltage applied in the first polarization direction followed by partial depolarization by a second voltage applied in a direction opposite to the first polarization direction. A second ferroelectric capacitor or a linear capacitor may be placed in parallel with the ferroelectric capacitor to form a two-capacitor memory cell. Data may be read to or from the capacitor cell without impairing the state of the stored data.

Abstract: A system and method for replacing sense amplifiers used in conventional RAMS with domino circuits in order to create a domino static random access memory. The domino SRAM of the present invention is created through extensive partitioning of conventional bit lines into local bit lines corresponding to the local cell groups within the SRAM. A ratioed inverter is coupled to each one of the local bit lines in a local cell group to form dynamic nodes and to provide a sense function for the local cell group. A tree-hierarchy of Or-gates is coupled to the ratioed inverters to complete the domino circuit.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of address detecting circuits capable of registering a defective address indicating a defective memory cell out of the plurality of memory cells for detecting whether an external address matches the defective address or not and each corresponding to 1 bit of the external address or complementary 1 bit thereof, and first and second terminals. Each of the address detecting circuits includes first and second capacitors each having a floating electrode formed of the same layer as a cell plate electrode of a memory cell, a fixed electrode formed of the same layer as a storage node electrode of the memory cell, and a dielectric layer formed of the same layer as a dielectric layer of the memory cell and formed between the floating electrode and the fixed electrode. If 2.times.Vcc is applied to the first terminal and 2.times.Vcc+.delta. is applied to the second terminal, charges are charged in the first and the second capacitors.

Abstract: A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode.

Abstract: A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings.

Abstract: A memory array for an electronic device comprises a design which requires fewer memory devices to be activated to access a plurality of data bits, thereby reducing the amount of power required to access the data bits. The design comprises the use of a plurality of memory devices, each of which has a plurality of arrays and data out lines.