Abstract: A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage which are coupled to the gate of a memory cell access transistor. Addressing circuitry is provided to selectively address the distributed local phase driver circuits.

Abstract: Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range.

Abstract: A bit line reference circuit for a nonvolatile semiconductor memory device performs a referenced data access operation using a single bit line having upper and lower portions. The circuit has an open bit line structure and includes an upper memory cell string connected to the upper portion of the bit line, and a lower memory cell string connected to the lower portion of the bit line. An upper reference cell string is connected to the upper bit line for providing a reference potential to the upper bit line in response to a first control signal, while the lower memory cell string is selected. A lower reference cell string is connected to the lower bit line for providing a reference potential to the lower bit line in response to a second control signal, while the upper memory cell string is selected. A page buffer is connected between the upper and lower portions of the bit line and accesses data by comparing the potentials on the upper and lower portions of the bit line.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is desclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof as permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory module includes a plurality of memory devices, each memory device including a plurality of memory cell arrays, a plurality of data input/output lines, and a memory cell array select input line. The plurality of memory cell arrays are arranged as a plurality of blocks such that data transfer is enabled between a memory cell array in each block of the plurality of blocks and a respective data input/output line of the plurality of data input/output lines when a predetermined voltage is applied to the memory cell array select input line. The module includes a circuit substrate on which the plurality of memory devices is mounted, the circuit substrate including first and second voltage busses.

Abstract: A non-volatile semiconductor memory device including a plurality of non-volatile memory cells and a plurality of reference cells provided for corresponding to storage states in the non-volatile memory cell, generating a reference current which is a current between two output currents of at least two reference cells or a current proportional to the current when data reading from the non-volatile memory cell, and comparing the reference current and a current from the non-volatile memory cell to read out a data stored in the non-volatile memory cell.

Abstract: In the semiconductor memory of this invention, a first unit of data that is inputted by means of the same standard clock as an external address and that is inputted to a chip prior to determination of the internal address signal that is prefetched is latched to all latch circuits into which this data may be latched. After an address is determined by the next standard clock, second and succeeding units of data inputted to the chip are inputted only to latch circuits that are latched in accordance with address signals. In this way, even if internal address signal processing has not been completed at the time of latching the first unit of data, both the first unit of data and second and succeeding units of data can be latched in prefetch circuits designated by addresses from the outside.

Abstract: A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.

Abstract: Inputted digital data are held in a data register and converted to multi-state analog amount by a resistance dividing circuit and a decoder. A comparator compares an analog amount read from a non-volatile memory cell with a converted analog amount; and in accordance with this comparison result, a writing voltage is supplied to a memory cell. A first bias generating circuit is provided for generating two different types of bias voltages as this writing voltage, MOS transistors are inserted as respective switches to the bias voltage supply lines and writing voltages are switched by selectively ON/OFF-controlling one of the MOS transistors in accordance with the upper bit of the inputted digital data. As a result, unnecessary writing time can be eliminated, time required for executing writing can be reduced and circuit configuration can be simplified.

Abstract: Integrated circuit memory devices with latch-free page buffers therein include a page buffer for electrically coupling a bit line from an array of memory cells to a buffer output. The page buffers generate a first logic state at an output thereof when the bit line is at a first logic potential and a high-impedance logic state when the bit line is at a second logic potential, during a memory read operation. An output buffer is also provided for converting the high-impedance state and the first logic state generated by the page buffer to respective opposite logic states (e.g, logic 1 and logic 0). The bit line data is used to directly trigger the appropriate state of the page buffer output by coupling a gate of an insulated-gate isolation transistor to the bit line data and then reading the source of the isolation transistor as the page buffer output.

Abstract: The present invention relates to a cache Static Random Access Memory, and includes an SRAM cell array unit having a 4 way.times.64 set cell array structure; a write circuit unit for renewing one bit line of 4 way.times.

Abstract: A switching circuit for switching a bit line potential VBL of a DRAM to a power supply potential Vcc, an intermediate potential Vcc/2 or the ground potential GND is provided. In normal operation, the bit line potential VBL is set to Vcc/2. In a special write mode, Vcc or GND is applied to all the bit lines through an equalizer, a desired word line is raised to "H" level, and Vcc or GND is written to the storage nodes of all the memory cells connected to the word line. It is possible to write Vcc or GND even to the storage node of a memory cell which has been replaced by a redundant memory cell.

Abstract: A nonvolatile semiconductor memory device comprises an electrically erasable programmable memory cell array, a write-only word line and read-only word line provided in a row direction of the memory cell array and connected to corresponding memory cells and a write-only data line and read-only data line provided in a column direction of the memory cell array and connected to the memory cells.

Abstract: An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline.

Abstract: Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit.

Abstract: An inhibition signal CAIHT for inhibiting, in adaptation to the data output timing of an output buffer, an internal column address strobe signal int/CAS output from a CAS buffer from falling from an H level to an L level for a prescribed period is generated and then applied to the CAS buffer. During data output, the internal column address strobe signal int/CAS is inhibited from being brought into an active state for the prescribed period, so that new data can be prevented from being transferred to the output buffer during this inhibition period, whereby erroneous data resulting from output noise can be prevented from being output. Consequently, a semiconductor memory device capable of correctly outputting data without the influence of the output noise is provided.

Abstract: A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

Abstract: In a semiconductor memory device, a data is written in a memory cell through a pair of digit lines during a write operation time interval. An equalizing operation is performed to the pair of digit lines in response to an equalizing control signal during the write operation time interval to recover potentials of the digit lines. In order to suppress output change of a sense amplifier circuit on the equalizing operation, a load of the sense amplifier circuit is changed in response to the equalizing control signal by a flip-flop circuit such that the load becomes heavier than that before the equalizing operation. The flip-flop circuit is composed of a flip-flop section, and first and second transfer gates connected between the outputs of the sense amplifier circuit and the inputs of the flip-flop section. The first and second transfer gates are set to the conductive state in response to the equalizing control signal.

Abstract: In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a time-staggered basis. In an eight bank embodiment, activation of a selected row is first initiated in Bank0 by registration of an ACTIVE command and a coincident row address. One system clock cycle later, activation of the selected row is initiated in Bank1, and so on until activation of the selected row is initiated in Bank7 seven clock cycles after the initial registration of the command. A READ or WRITE command and coincident column address can be applied after the activation time limit has been met for the selected row in Bank0. The READ or WRITE command then affects successive banks in the above-described time staggered manner.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence.