Patents Examined by Joseph Schell
  • Patent number: 9311201
    Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
  • Patent number: 9304873
    Abstract: Embodiments include a recovery system, a computer-readable storage medium, and a method of recreating a state of a datacenter. The embodiments include a plurality of program modules that is executable by a processor to gather metadata from a first datacenter that includes at least one virtual machine (VM), wherein the metadata includes data representative of a virtual infrastructure of the first datacenter. The program modules are also executable by the processor to recreate a state of the first datacenter within a second datacenter using the metadata upon a determination that a failure occurred within the first datacenter, and to recreate the VM within the second datacenter.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: April 5, 2016
    Assignee: VMware, Inc.
    Inventors: Glenn Bruce McElhoe, Orran Krieger, Philip McGachey
  • Patent number: 9304935
    Abstract: Performing a transaction in a transactional memory environment for performing transactional executions, the transactional memory environment including a digest-generating transaction to generate a computed digest and a digest-checking transaction to compare computed digests is provided.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura
  • Patent number: 9304844
    Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kapil Bansal, Girish Bhat, Subodh Singh, Victor Wong, Pradeep Atur
  • Patent number: 9304884
    Abstract: A test apparatus applicable to a server includes a processing unit, a control unit, a switch unit and a power relay unit. The processing unit outputs a reset signal and a processing signal. The control unit includes a first physical layer chip performing a first communication protocol, and a second physical layer chip performing a second communication protocol. The switch unit receives a working voltage and a processing signal to select a powering signal or a disconnection signal to output. The power relay unit receives the powering signal or the disconnection signal. When the power relay unit receives the powering signal, the server performs a test task on the first physical layer chip. When the power relay unit receives the disconnection signal and the processing unit outputs the reset signal to the control unit, the server performs the test task on the second physical layer chip.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: April 5, 2016
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Chun-Hao Chu
  • Patent number: 9298524
    Abstract: A system firmware agent providing the capabilities of a Baseboard Management Controller (BMC) from within System Management Mode (SMM) is discussed. A virtual BMC provides dedicated communication channels for system firmware, other BMCs in the platform and remote management agents. The virtual BMC may monitor the status of the system, record system events, and control the system state.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 29, 2016
    Assignee: Insyde Software Corp.
    Inventor: Timothy Andrew Lewis
  • Patent number: 9298538
    Abstract: This disclosure presents systems and methods for run-time analysis of streams of log data for abnormalities using a statistical structure of meta-data associated with the log data. The systems and methods convert a log data stream into meta-data and perform statistical analysis in order to reveal a dominant statistical pattern within the meta-data. The meta-data is represented as a graph with nodes that represent each of the different event types, which are detected in the stream along with event sources associated with the events. The systems and methods use real-time analysis to compare a portion of a current log data stream collected in an operational window with historically collected meta-data represented by a graph in order to determine the degree of abnormality of the current log data stream collected in the operational window.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 29, 2016
    Assignee: VMware, Inc.
    Inventors: Mazda A. Marvasti, Arnak Poghosyan, Ashot Harutyunyan, Naira Grigoryan
  • Patent number: 9292289
    Abstract: Performing a transaction in a transactional memory environment for performing transactional executions, the transactional memory environment including a digest-generating transaction to generate a computed digest and a digest-checking transaction to compare computed digests is provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura
  • Patent number: 9268670
    Abstract: Systems and methods are described for generating a test executable used for testing an application locally on a host device. A user interface allows selection of particular test modules for use. Based on the selected modules a test executable is generated. The test executable functionality may integrated with the application or be independent of the application. The host device executes the test executable which enables testing and debugging on the local device.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: February 23, 2016
    Assignee: Google Inc.
    Inventors: Manish Lachwani, Jay Srinivasan, Pratyus Patnaik, Timothy D. Wang
  • Patent number: 9264780
    Abstract: Managing synchronized data requests is disclosed. Examples of synchronized data requests include viewer-induced synchronization, failure-induced synchronization, and player-induced synchronization. Information indicative of the potential occurrence of a detrimental amount of synchronized requests in a content delivery infrastructure is received. One or more remediation actions is automatically caused to occur.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: February 16, 2016
    Assignee: Conviva Inc.
    Inventors: Ion Stoica, Hui Zhang, Aditya R. Ganjam
  • Patent number: 9258202
    Abstract: A network system comprising logical work and protect Connection Termination Points. Performance Monitoring (PM) records are provided by generating for each work Connection Termination Point (CTP) a work bit vector and a protect bit vector. The work bit vector keeps track of severely errored seconds (SES) occurrences at the work CTP only when the work CTP is selected. The protect bit vector keeps track of severely errored seconds (SES) occurrences at the protect CTP only when the protect CTP is selected. Processing the work bit vector and the protect bit vector provides accurate PM records.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: February 9, 2016
    Assignee: Ciena Corporation
    Inventors: Simmon Yau, Satish M. Gopalakrishna, Yossi Joseph Khalon, Matthew W. Connolly
  • Patent number: 9251015
    Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: February 2, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Tae Yim, Sung-Kue Jo
  • Patent number: 9251003
    Abstract: A database system may implement database cache survivability across database failures. In various embodiments, a database cache may be maintained independent of a failure of a database. A database cache may be maintained in a non-volatile memory device or maintained in a shared memory segment of system memory. Upon recovery from a database failure, a recovery point may be determined that indicates a consistent state of the database. Cache entries of the database cache inconsistent with the consistent state of the database may be invalidated, and the database cache may be made available for access requests directed toward the database. Valid cache entries from before the database failure may be made available without accessing a back-end data store for the database.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: February 2, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Anurag Windlass Gupta, Pradeep Jnana Madhavarapu, Matthew David Allen, Laurion Darrell Burchall, James McClellan Corey
  • Patent number: 9244771
    Abstract: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and outputs of the primary instance and gates those inputs to the backup instance once a given input has been processed. The outputs of the backup instance are then compared with the outputs of the primary instance to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup instance to take over for the primary instance in a fault situation wherein the primary and backup instances are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: January 26, 2016
    Assignee: Chicago Mercantile Exchange Inc.
    Inventors: Paul J. Callaway, Robert C. Hagemann, III, Zuber Shethwala, Troy Reece, Paul Andrew Bauerschmidt, Enrico Ferrari
  • Patent number: 9244758
    Abstract: Systems and methods are provided for repairing system files. For example, a list of system files including file information of one or more first repairable system files are updated in real time; file information of a target file sent from a terminal is received; whether the target file is in need of repair is detected based on at least information associated with the list of system files; in response to the target file being in need of repair, a first repair strategy for the target file is determined based on at least information associated with a predetermined database of repair strategies and a file type of the target file; and the target file is repaired based on at least information associated with the first repair strategy.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 26, 2016
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Rui Zhou, Shuai Rao
  • Patent number: 9235485
    Abstract: In an embodiment, a partition is executed at a primary server, wherein the partition accesses a first memory location at a first memory block address at the primary server. If a first corresponding memory location at a secondary server has an error, wherein the first corresponding memory location at the secondary server corresponds to the first memory location at the primary server, then an object is moved from the first memory location at the primary server to a second memory location at the primary server.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: January 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, David A. Larson
  • Patent number: 9229805
    Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Tae Yim, Sung-Kue Jo
  • Patent number: 9229845
    Abstract: Proposed updates to systems are evaluated in a manner that is automated and horizontally scalable. Input to a first system is provided to a second system. The first system and second system process the input and each generates output. The output from the first system and second system is analyzed and differences in the output data between the two systems are identified. Analyzing the output may be performed by a fleet of data processing units and the work of analyzing the output may be performed such that differences in the output data are traceable to subsystems of the second system that caused the differences.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 5, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Ramakrishnan Hariharan Chandrasekharapuram, Carlos Alejandro Arguelles
  • Patent number: 9223669
    Abstract: A method for automatically testing an apparatus controlled by software based on pilot test case file comprising user input sequence data recorded manually and the time stamp of the input. In the process of automated testing, these pre-recorded user inputs are replay with same input sequence but with either the same time interval between two subsequent inputs recorded prior; or with a random time interval autonomously generated in a range set by the test configuration. During the process of replaying user input, a separate plural numbers of background tasks are executed in parallel with random execution delays to generate varying system load and execution timing to simulate the apparatus' unpredictable real operation scenarios. The user input and new random time interval between each user input are recorded at replay as a new expanded test record file for later test result trace and failure analysis.
    Type: Grant
    Filed: January 7, 2012
    Date of Patent: December 29, 2015
    Inventor: Robert Lin
  • Patent number: 9223678
    Abstract: Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William C. Moyer, Jeffrey W. Scott