Patents Examined by Joseph Schoenholtz
  • Patent number: 10283440
    Abstract: A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-contro
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 7, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 10276815
    Abstract: This invention provides a transistor device structure that incorporates a self-aligned doped contact formed by inserting a molecularly-thin layer of bonded anions between the semiconductor and the source-drain electrode array wherein the semiconductor is p-doped at the interface with the bonded-anion layer, and a method of making this structure using oxidant species incorporated into the molecularly-thin layer. The device shows ohmic hole injection and hole extraction at the contacts to give high-performance transistor characteristics with low contact resistance.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 30, 2019
    Assignees: BASF SE, National University of Singapore
    Inventors: Mi Zhou, Peter K.-H. Ho, Lay-Lay Chua, Png Rui-Qi, Wei-Ling Seah
  • Patent number: 10269923
    Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Wei-Hao Lee, Huan-yu Shih
  • Patent number: 10270057
    Abstract: A light-emitting element, a bonding layer, and a frame-like partition are formed over a substrate. The partition is provided to surround the bonding layer and the light-emitting element, with a gap left between the partition and the bonding layer. A pair of substrates overlap with each other under a reduced-pressure atmosphere and then exposed to an air atmosphere or a pressurized atmosphere, whereby the reduced-pressure state of a space surrounded by the pair of substrates and the partition is maintained and atmospheric pressure is applied to the pair of substrates. Alternatively, a light-emitting element and a bonding layer are formed over a substrate. A pair of substrates overlap with each other, and then, pressure is applied to the bonding layer with the use of a member having a projection before or at the same time as curing of the bonding layer.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 10262294
    Abstract: A user may pick, place, or move an item at an inventory location, such as a shelf. Described are techniques to determine a location of one or more of an object, such as an item or a user, with respect to an array of capacitive sensors. The array may be part of the shelf. As an item is added to, moved or removed from the shelf, when the user's hand is near the shelf, and so forth, capacitance measured by one or more of the sensors in the array may change. Based on these changes, a location relative to the sensor array may be determined. A particular shelf may have different areas, each designated as holding a different type of item. The location information obtained from the capacitive sensors may be used to determine which item on the shelf was interacted with.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: April 16, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Camerin Cole Hahn, Qicai Shi, Christopher Raymond Grajewski, Vinod Lakhi Hingorani, Nathan Pius O'Neill
  • Patent number: 10256349
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 10256221
    Abstract: Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Apple Inc.
    Inventors: Andreas Bibl, Charles R. Griggs
  • Patent number: 10256284
    Abstract: A display device includes: a substrate including a bending area located between a first region and a second region; an organic layer disposed over the substrate, an upper surface of the organic layer including an uneven surface in the bending area, the uneven surface including a plurality of protrusions; and a conductive layer extending from the first region to the second region across the bending area, the conductive layer being located over the organic layer and including a plurality of through holes.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoonsun Choi, Wonsuk Choi, Cheolsu Kim, Sangjo Lee
  • Patent number: 10249611
    Abstract: A diode string for a semiconductor circuit configured with a guard ring silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection. The diode string includes multiple NPN transistor diode structures formed in an N-well structure and electrically coupled in series between a reference voltage node and an I/O pad. Each diode structure may include a P-type retro-well structure including at least one N+ doped region and at least one P+ doped region. The P+ guard ring includes at least one P+ doped structure formed in the N-well structure disposed on either side of the first diode structure and electrically coupled to the reference voltage node. The P+ guard ring forms the SCR with the first diode structure. The diode string is triggered in response to an ESD event, which activates the SCR, and the SCR clamps the I/O pad to the reference voltage node and handles the ESD current.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 2, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Yunfeng Xi, Jeremy C. Smith
  • Patent number: 10249718
    Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Patent number: 10243103
    Abstract: Embodiments relates to an ultraviolet light emitting diode, a method of manufacturing an ultraviolet light emitting diode, a light emitting diode package, and a LIGHTING DEVICE. An ultraviolet light emitting diode according to an embodiment includes: a substrate; a first undoped GaN layer including a planar upper surface and a V-pit on the substrate; a first nitride layer on the V-pit of the first undoped GaN layer; a first undoped AlGaN-based semiconductor layer on the first undoped GaN layer and the first nitride layer; and a second undoped GaN layer on the first undoped AlGaN-based semiconductor layer, wherein the first undoped AlGaN-based semiconductor layer includes a first region on the planar upper surface of the first undoped GaN layer and a second region located on the V-pit of of the first undoped GaN layer, and wherein an Al concentration of the first region may be greater than that of the second region.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 26, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Chan Keun Park
  • Patent number: 10243124
    Abstract: A light emitting device includes a light emitting element having a light emitting surface from which the light emitting element is configured to emit a first light having a first peak emission wavelength in a wavelength range of 380 nm or longer and 430 nm or shorter. A light transform layer is disposed on the light emitting surface of the light emitting element to transform the first light to a second light having a second peak wavelength longer than the first peak wavelength. A reflecting film is provided on the light transform layer to reflect the first light and to transmit the second light. The reflecting film has a reflectivity of 40% or more in a reflection spectrum of the reflecting film with respect to a light having a wavelength of 380 nm or longer and 430 nm or shorter and an angle of incidence from 0° to 85°.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Taiki Yuasa, Takeshi Kususe
  • Patent number: 10242957
    Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, David Francis Berdy, Chengjie Zuo, Jonghae Kim, Matthew Michael Nowak
  • Patent number: 10234163
    Abstract: At least one aspect of the present disclose is directed towards a temperature control device that includes a face plate, a housing, and an adjustment mechanism. The housing may protrude away from the rear side of the face plate. The housing may include a mounting mechanism that includes a set of clamps configured to engage at least a portion of an inner surface. The set of clamps may be adjustable based on alterations to the adjustment mechanism. The housing may also include one or more cavities that may be configured to receive at least a portion of the set of clamps when the set of clamps is collapsed into the housing.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 19, 2019
    Assignee: Alarm.com Incorporated
    Inventor: Gary Franklin Bart
  • Patent number: 10229931
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory stack structures through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures, forming a backside blocking dielectric layer in the backside recesses, forming an amorphous titanium oxide layer on surfaces of the backside blocking dielectric layer in the backside recesses, and forming tungsten word lines in the backside recesses using a fluorine-free tungsten-containing precursor gas.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 12, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Hinoue, Tomoyuki Obu
  • Patent number: 10224515
    Abstract: Discussed herein is an organic light-emitting display (OLED) device that may include an organic light-emitting element layer disposed on a substrate; and an encapsulation layer covering the organic light-emitting element layer to block moisture and/or oxygen from permeating, wherein the encapsulation layer includes a barrier film having at least one transmittance adjusting layer that adjusts a ratio at which light emitted from the organic light-emitting element layer exits the OLED device, whereby the use of a polarizer is avoided.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 5, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Heechul Lim, GyuHyeong Han
  • Patent number: 10224483
    Abstract: A crosslinkable quantum dot (QD) and a preparing method thereof, an array substrate made by using the crosslinkable quantum dot (QD) and a preparing method thereof are provided. The surface of the crosslinkable quantum dot has a pair of groups R1 and R2 capable of reacting to form a cross-linked network, or a group R3 capable of being cross-linked by a crosslinking agent to form a cross-linked network.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 5, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yanzhao Li, Zhuo Chen, Yuedi He, Jie Sun
  • Patent number: 10217895
    Abstract: The present disclosure provides a method of forming a light-emitting device comprising: providing a growth substrate having a front side and a rear side; forming a sacrificial layer on the front side of the growth substrate; forming a protective structure on the sacrificial layer; forming a light-emitting structure on the protective structure, wherein the light-emitting structure emits a first peak wavelength; providing a carrier; joining the carrier and the light-emitting structure; and transforming the sacrificial layer by irradiating a laser beam from the rear side to separate the growth substrate from the light-emitting structure, wherein the laser beam emits a second peak wavelength, and wherein the protective structure reflects the second peak wavelength away from the light-emitting structure.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: February 26, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-hao Chen, Yi-Lun Chou, Wei-Chih Peng
  • Patent number: 10217632
    Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Kuen-Ting Shiu
  • Patent number: 10217882
    Abstract: A quantum rod, a synthesis method of the quantum rod and a quantum rod display device are discussed. The quantum rod according to an embodiment includes a core, a first shell covering the core, and a second shell covering a side of the first shell. In the quantum rod, a first thickness of the first shell is greater than a second thickness of the second shell, and a first length of the first shell is smaller than a second length of the second shell.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 26, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kyung-Kook Jang, Byung-Geol Kim, Wy-Yong Kim, Kyu-Nam Kim, Sung-Il Woo