Abstract: Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.

Abstract: The disclosure provides a light-emitting device. The light-emitting device comprises: a substrate having a first patterned unit; and a light-emitting stack on the substrate and having an active layer with a first surface; wherein the first patterned unit, protruding in a direction from the substrate to the light-emitting stack, has side surfaces abutting with each other and substantially non-parallel to the first surface in cross-sectional view, and has a non-polygon shape in top view.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract: The reliability of a semiconductor device including a power semiconductor element is improved. The basic idea in embodiments is to make the band gap of a cell region smaller than the band gap of a peripheral region. Specifically, a lower band gap region having a smaller band gap than the band gap of an epitaxial layer is formed in the cell region. In addition, a higher band gap region having a larger band gap than the band gap of the epitaxial layer is formed in the peripheral region.

Abstract: A nitride semiconductor power device includes an AlGaN multilayer, which has changeable Al composition along a depositing direction, and SixNy layer, so as to minimize an increase in a leakage current and a decrease in a breakdown voltage, which are caused while fabricating a heterojunction type HFET device. A semiconductor device includes a buffer layer, an AlGaN multilayer formed on the buffer layer, a GaN channel layer formed on the AlGaN multilayer, and an AlGaN barrier layer formed on the AlGaN multilayer, wherein aluminum (Al) composition of the AlGaN multilayer changes along a direction that the AlGaN multilayer is deposited.

Abstract: A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 m?·cm to about 12000 m?·cm both inclusive.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a gate structure formed on a substrate, a source/drain extension formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a first type impurity, a halo region formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a second type impurity different from the first type impurity, a first source/drain region formed at one side of the gate structure and doped with the first type impurity, and a second source/drain region formed at the other side of the gate structure and doped with the first type impurity.

Abstract: A pixel array includes a plurality of pixel groups, each of which includes a plurality of brightness sub-pixel regions, a plurality of first sub-pixel regions, and a plurality of second sub-pixel regions. Each brightness sub-pixel regions has a first side, a second side, a third side, and a fourth side. The first sub-pixel regions include a first group and a second group, and the second sub-pixel regions include a third group and a fourth group. The first, the second, the third, and the fourth groups are respectively disposed at the first, the third, the second, and the fourth sides of the first brightness sub-pixel region. Extension lines of long directions of the first, the second, the third, and the fourth groups respectively interlace a vertical baseline at a first angle ?1, a second angle ?2, a third angle ?3, and a fourth angle ?4. 0°<?1<90°, 0°<?2<90°, 0°<?3<90°, and 0°<?4<90°.

Abstract: Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

Abstract: A light receiving element includes a p-type semiconductor layer, an n-type semiconductor layer, and a first and a second superlattice semiconductor layers, and the first and the second superlattice semiconductor layers each have a superlattice structure in which a barrier layer and a quantum dot layer are alternately and repeatedly stacked. A band structure of the superlattice structure of the first superlattice semiconductor layer is a type I structure, and that of the second superlattice semiconductor layer is a type II structure. The superlattice structures of the first and the second superlattice semiconductor layers each form a superlattice miniband, and a conduction band first superlattice miniband of the superlattice structure of the second superlattice semiconductor layer is lower in lower and energy than a conduction band first superlattice miniband of the superlattice structure of the first superlattice semiconductor layer.

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.

Abstract: There is provided a light emitting apparatus provided with a pixel circuit which is provided with a plurality of transistors including a first transistor and a light emitting element in which a current is supplied by the first transistor, in which, in at least one of the plurality of transistors, a wiring is connected to a gate electrode at a position overlapping a channel region in plan view.

Abstract: An integrated circuit includes a substrate having a plurality of electronic devices, a plurality of interconnect layers disposed on one or both sides of the substrate, and a plurality of active electrically conductive interconnect layer structures. The plurality of interconnect layers include horizontal interconnect and vertical-interconnect-access (VIA) layers. The plurality of active electrically conductive interconnect layer structures are disposed on at least one of the plurality of interconnect layers and electrically coupled with at least one of the plurality of electronic devices. The integrated circuit also includes a plurality of spare electrically conductive interconnect layer structures disposed on at least one of the plurality of interconnect layers and electrically isolated from the plurality of active electrically conductive interconnect layer structures.

Abstract: An organic light-emitting device may include a substrate; an anode on the substrate; a hole transport region on the anode; an emission layer on the hole transport region; an electron transport region on the emission layer; and a cathode on the electron transport region. The electron transport region may include an electron injection layer including a first component which is a salt chloride and a second component which is at least one metal selected from ytterbium (Yb), scandium (Sc), vanadium (V), yttrium (Y), indium (In), cerium (Ce), samarium (Sm), europium (Eu), and terbium (Tb). In addition, the cathode may contacts the electron injection layer and may include an alloy of a first cathode metal including at least one of Ag, Au, Pt, Cu, Mn, Ti, Co, Ni, and W, and a second cathode metal including least one of Yb, Sc, V, Y, In, Ce, Sm, Eu, and Tb.

Abstract: A pixel substrate and a fabrication method thereof are provided. The method includes: forming a gate and a lower pad on a substrate; forming a gate insulating layer overlaying the gate and the lower pad; forming a channel layer and a first electrode layer on the gate insulating layer, in which the projection areas of the channel layer and the gate on the substrate are overlapped; forming an etching-barrier material layer on the substrate and simultaneously forming a contact opening at the gate insulating layer to expose the lower pad; forming a source, a drain and an upper pad on the substrate; forming a protective layer; forming a second electrode layer with multiple slits on the protective layer, in which one of the first and second electrode layers is electrically connected to the drain. The invention can simplify the process steps and reduce fabrication time.

Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor, which can display a high-definition image and can be manufactured with a high yield. The semiconductor device includes a pixel portion including a plurality of pixels, a gate signal line driver circuit portion, and a source signal line driver circuit portion including a first circuit that controls timing of sampling video signals and a second circuit that samples the video signals in accordance with the timing and then inputs the sampled video signals to the pixels. The second circuit includes a plurality of transistors in each of which an oxide semiconductor stacked layer is used as a channel formation region, the first circuit and the second circuit are electrically connected to each other by a wiring, and the wiring is electrically connected to gates of at least two transistors of the plurality of transistors.

Abstract: A vertical probe card includes a bottom substrate, a top substrate, an interposer, a first set of electrically conductive polymer contacts, a second set of electrically conductive polymer contacts, a first anisotropic conductive film, and a second anisotropic conductive film. The interposer is disposed between the bottom substrate and the top substrate. The first set of electrically conductive polymer contacts is disposed on the surface of the bottom substrate opposite to the interposer. The second set of electrically conductive polymer contacts is disposed on the surface of the top substrate opposite to the interposer. The first set of electrically conductive polymer contacts are arranged differently from the second set of electrically conductive polymer contacts. The first anisotropic conductive film is disposed between the bottom substrate and the interposer, and configured to electrically connect the bottom substrate and the interposer.

Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly having a cathode electrode, a N+ substrate layer on the cathode electrode, a N buffer layer on the N+ substrate layer, and a N? bulk layer on the N buffer layer. The N buffer layer may include crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer on a N+ substrate wafer, creating a N? bulk layer on the N buffer layer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer in a N? bulk wafer, creating a N+ substrate layer in the N? bulk wafer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers.