Patents Examined by Juanita Rhodes
  • Patent number: 10256171
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10243167
    Abstract: A an organic light-emitting display apparatus, including a first substrate, a display unit having a plurality of organic light-emitting devices that is formed on the first substrate, a second substrate disposed on the display unit, and a filler included between the first substrate and the second substrate. The organic light-emitting device includes a first electrode formed on the first substrate, an intermediate layer that is disposed on the first electrode and includes an organic emission layer, and a porous second electrode disposed on the intermediate layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 26, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 10242933
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10217659
    Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 10211423
    Abstract: A an organic light-emitting display apparatus, including a first substrate, a display unit having a plurality of organic light-emitting devices that is formed on the first substrate, a second substrate disposed on the display unit, and a filler included between the first substrate and the second substrate. The organic light-emitting device includes a first electrode formed on the first substrate, an intermediate layer that is disposed on the first electrode and includes an organic emission layer, and a porous second electrode disposed on the intermediate layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: February 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 10199278
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein a hardmask is formed on each of the plurality of fins, forming a gate structure around the plurality of fins, selectively depositing a dummy dielectric on the hardmask on each of the plurality of fins, depositing a dielectric layer on the gate structure and around the dummy dielectrics, selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure to create a plurality of openings exposing portions of the gate structure, and selectively removing the exposed portions of the gate structure through the plurality of the openings.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10197868
    Abstract: A display device includes a first substrate having a first lower column spacer disposed in a peripheral area, extending in a direction, and including first and second opposing slanted sides, a second substrate opposing the first substrate, the second substrate including a first upper column spacer disposed in the first peripheral area, extending in the same direction, including a slanted side, and disposed adjacent to the first side of the first lower column spacer, and a second upper column spacer having substantially a same shape as the first upper column spacer and disposed adjacent to the second side of the first lower column spacer, where the first peripheral area is disposed outside a display area of the display device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Hoon Jung, Hyangyul Kim, Hyoung-Joon Kim
  • Patent number: 10192833
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
  • Patent number: 10177190
    Abstract: A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 8, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Yuichiro Yamashita, Masahiro Kobayashi
  • Patent number: 10177076
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10163956
    Abstract: An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10164161
    Abstract: A light emitting arrangement is suggested for generating directional projections of light with sharply defined beam profile. Light from a top-emitting solid state light source (12), having reflective side-coating (34), is pre-collimated via a beam-shaping optic (16), before being propagated through a secondary collimating funnel (18), capturing any light rays with still too great an escape angle. Chip-scale package dimensions may be achieved through the use of a thin-film side-coating and undersized phosphor layers. Substrate level process flow further allows for parallel processing of a plurality of devices.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 25, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Norbertus Antonius Maria Sweegers, Floris Maria Hermansz Crompvoets, Marc Andre De Samber
  • Patent number: 10163952
    Abstract: A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chan Chen, Yueh-Chuan Lee, Chih-Huang Li, Ta-Hsin Chen
  • Patent number: 10153431
    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P. Marsh, Jun Liu
  • Patent number: 10153269
    Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm?3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 11, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew D. Strachan, Alexei Sadovnikov, Gang Xue, Dening Wang
  • Patent number: 10147775
    Abstract: A display substrate, a method of manufacturing the same, and a display device including the display substrate disclosed. In one aspect, the display substrate includes a pixel circuit disposed over a base substrate, an insulation layer disposed over the base substrate and overlapping the pixel circuit in the depth dimension of the display substrate, and a pixel electrode disposed over the insulation layer and electrically connected to the pixel circuit. The display substrate also includes a pixel defining layer disposed over the insulation layer, the pixel defining layer formed over a portion of the pixel electrode, and a spacer structure including a first spacer and a second spacer disposed over the first spacer, the first spacer being separated from the pixel circuit and disposed over the insulation layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Hyun Kim, Sung-Kyun Park, Jeong-Min Park
  • Patent number: 10147675
    Abstract: A semiconductor device includes a base including a substrate and a first insulating layer formed thereon. The base has a first surface and a second surface that is opposite to the first surface, and has an opening that passes through from the first surface to the second surface. A first width of the opening at the first surface is greater than a second width of the opening at the second surface. An electrode formed on the second surface of the base and covers the opening. A metal layer fills the opening and is electrically connected to the electrode.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 4, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Toshiro Mitsuhashi
  • Patent number: 10134736
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 20, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10128273
    Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 13, 2018
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chung Su, Po-Hsueh Chen, Yi-Wei Chen, Hsiu-Chun Hsieh
  • Patent number: 10115701
    Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 30, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xing Zhao, Duk Ju Na, Siew Joo Tan, Pandi C. Marimuthu