Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate an array substrate, which can avoid poor displays due to large coupling capacitance between a data line and a pixel electrode in an array substrate in the prior art. The manufacturing method comprises the following steps: S1, forming a data line metal layer on a substrate, and forming a pattern of a data line by a patterning process; S2, forming a semiconductor layer on the substrate formed with the data line thereon, and forming a pattern of an active layer by a patterning process, wherein the data line is connected with the active layer.

Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.

Abstract: A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0).

Abstract: A liquid crystal display includes a gate line and a data line disposed on a substrate, a reference voltage line aligned with the data line, and a plurality of pixels arranged substantially in a matrix form. In such a liquid crystal display, each pixel includes a first sub-pixel, a second sub-pixel, and a driving unit electrically connected to the gate line, the data line and the reference voltage line. In such a liquid crystal display, one reference voltage line is disposed between two adjacent pixels.

Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.

Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

Abstract: A method of forming a flexible display apparatus includes: forming a flexible substrate on a support substrate; forming a light-emitting diode on the flexible substrate; forming a first encapsulation layer on the light-emitting diode; forming a second encapsulation layer; bonding the first encapsulation layer to the second encapsulation layer using an adhesive layer between the first encapsulation layer and the second encapsulation layer; separating the support substrate from the flexible substrate and cutting the flexible substrate to form the flexible display apparatus; and forming a polarizing plate on the second encapsulation layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: A semiconductor device includes a semiconductor body with a first main crystal direction parallel to a horizontal plane. Longitudinal axes of trench gate structures are tilted to the first main crystal direction by a tilt angle of at least 2 degree and at most 30 degree in the horizontal plane. Mesa portions are between neighboring trench gate structures. First sidewall sections of first mesa sidewalls are main crystal planes parallel to the first main crystal direction. Second sidewall sections tilted to the first sidewall sections connect the first sidewall sections.

Abstract: In one embodiment of the present disclosure, a method for depositing metal in a feature on a workpiece is provided. The method includes electrochemically depositing a second metal layer on a first metal layer on a workpiece having at least two features of two different sizes in a dielectric layer, wherein the second metal layer is a copper layer and wherein the first metal layer includes a metal selected from the group consisting of cobalt and nickel, wherein the first metal layer completely fills the smallest feature but does not completely fill the largest feature.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Abstract: A microsystem includes a base layer formed from an electrical insulating material. The base layer has an inner surface defining a cavity and an external surface opposed to the inner surface, and in direct communication with an environment. A cap layer and a microelectromechanical (MEMS) device layer are formed from electrical insulating material or an other electrical insulating material. The cap has an inner surface defining a cavity, and an external surface opposed to the inner surface, and in direct communication with the environment. A MEMS device on/in the MEMS device layer is disposed between the base and the cap. Respective adjacent portions of the base, the cap and the device substrate are bonded to define an enclosed space. The enclosed space at least partially includes the base cavity or the cap cavity. At least a portion of a MEMS device on the device layer is in the enclosed space.

Abstract: A thin film circuit includes a thin film transistor with a metal oxide semiconductor channel having a conduction band minimum (CBM) with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band minimum (CBM) with a second energy level. The second energy level being lower than, equal to, or no more than 0.5 eV above the first energy level. The circuit is used for an electronic device including any one of an AMLCD, AMOLED, AMLED, AMEPD.

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm?3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.

Abstract: Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Abstract: A wide-angle emitting LED driven by built-in power and an assembling method are provided. The wide-angle emitting LED includes a transparent substrate, at least one light-emitting chip, and a driving circuit component. The front of the transparent substrate is provided with a printed circuit where a portion of an upper surface of the transparent substrate is provided with a plurality of conductive bonding pads. Each of the at least one light-emitting chip is bonded on the front of the transparent substrate, and the at least one light-emitting chip is electrically connected to the conductive bonding pads by metal wires. In addition, the driving circuit component is bonded with the transparent substrate and the conductive bonding pads and is electrically connected to the conductive bonding pads by metal wires.