Abstract: A display device is provided and includes a supporting substrate, a first flexible substrate, an oxide layer, a first insulating layer, a light emitting unit, and a protective layer. The first flexible substrate is disposed on the supporting substrate, and the oxide layer is disposed on the first flexible substrate. The first insulating layer is disposed on the oxide layer, and in a cross-sectional view, the first insulating layer has at least one opening. The light emitting unit is disposed on the first insulating layer, the protective layer is disposed on the light emitting unit, and at least a portion of the protective layer is disposed in the at least one opening.

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

Abstract: Provided is a power semiconductor device including a signal terminal and a power semiconductor element. The power semiconductor element is arranged on a substrate. The signal terminal includes a main body portion and a joint portion, and a part of the signal terminal is held by a terminal block. The joint portion includes a distal end portion and a base portion. The distal end portion includes a pad portion that is exposed from the terminal block and connected to a signal line. The base portion includes a thin portion in which a thickness in a vertical direction is set to be smaller than that of the pad portion. The thin portion has an upper surface that is formed at a position lower than an upper surface of the pad portion and is covered with a resin material forming the terminal block.

Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

Abstract: An image sensor may include an array of imaging pixels. Each imaging pixel may have a photosensitive area that is covered by a microlens and a diffractive lens that focuses light onto the photosensitive area. The diffractive lens may be interposed between the microlens and the photosensitive area. The diffractive lens may have a higher index of refraction than the surrounding materials. The diffractive lens may be formed as a portion of an anti-reflection coating. In some cases, multiple diffractive lenses may be formed over the imaging pixels. Focusing and defocusing diffractive lenses may be used to tune the response of the imaging pixels to incident light.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a base substrate, a metal pattern layer, a data line pattern layer, and a scan line pattern layer. Wherein, the data line pattern layer or the scan line pattern layer and the metal pattern layer are arranged in different layers and are directly connected to the metal pattern layer. So that the data line pattern layer or the scan line pattern layer and the metal pattern layer are formed a parallel structure. Because the resistance of the parallel structure is smaller than the resistance of the data line pattern layer or the scan line pattern layer, the resistance of the parallel structure when is used as a data line or a scan line, is reduced, thereby the display effect is improved.

Abstract: The present disclosure describes methods and patterned devices for reducing a loading effect between a low pattern density region and a high pattern density region. The patterned device includes a substrate, a first insulating layer over the substrate, a low pattern density region, a high pattern density region, a second insulating layer, and an epitaxial grown layer. The low pattern density region includes a first trench in the first insulating layer and the substrate. The high pattern density region includes a second trench in the first insulating layer and the substrate. The second insulating layer is formed in the first trench. The epitaxial grown layer is formed in the second trench. The first trench has a larger cross-sectional area than the second trench.

Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.

Abstract: The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: A method of manufacturing a photoelectric conversion apparatus includes heating a semiconductor substrate while a pixel circuit area is covered with an insulator film, performing ion implantation into the pixel circuit area through the insulator film, performing ion implantation into a peripheral circuit area after the heating, and forming a side wall on a side surface of a gate electrode of a transistor after the performing ion implantation into the peripheral circuit area.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

Abstract: An organic EL display apparatus (100) has a plurality of pixels including red pixels (R), green pixels (G) and blue pixels (B), the apparatus (100) including: a substrate (1); a plurality of organic EL elements (10) supported on the substrate, with one organic EL element provided in each pixel; a generally lattice-shaped first bank (21) defining the pixels, the first bank including a plurality of first portions (21A) extending in a first direction and a plurality of second portions (21B) extending in a second direction that crosses the first direction; and a plurality of second banks (22) provided on a top portion (21t) of the first bank, wherein the second banks are not formed at intersections (cr) between the first portions and the second portions of the first bank, and the second banks are more liquid repellent than the first bank.

Abstract: An organic EL display device (100) including a plurality of pixels includes an element substrate (1) including a substrate, and a plurality of organic EL elements supported by the substrate and respectively located in the plurality of pixels; and a thin film encapsulation structure (10) covering the plurality of pixels. The thin film encapsulation structure includes a first inorganic barrier layer (12), an organic barrier layer (14) in contact with a top surface of the first inorganic barrier layer (12), the organic barrier layer (14) including a plurality of solid portions distributed discretely, and a second inorganic barrier layer (16) in contact with the top surface of the first inorganic barrier layer (12) and top surfaces of the plurality of solid portions of the organic barrier layer (14). The organic barrier layer (14) exhibits a chromatic color.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.