Abstract: The present invention relates to a composition comprising a nanosized light emitting material, and method for preparing of said composition. The present invention further relates to a light luminescent medium, a light emitting device, the present invention further more relates to method for preparing of a composition and to method for preparing of a light emitting medium.

Abstract: A thin-film transistor according to an embodiment of the present invention includes: a gate electrode; an active layer formed of an oxide containing indium, zinc, and titanium; a gate insulating film formed between the gate electrode and the active layer; and a source electrode and a drain electrode that are electrically connected to the active layer. Atomic proportions of elements relative to the total quantity of indium, zinc, and titanium that constitute the oxide may be not less than 24 at. % and not more than 80 at. % for indium, not less than 16 at. % and not more than 70 at. % for zinc, and not less than 0.1 at. % and not more than 20 at. % for titanium.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

Abstract: Described herein is a technique capable of forming a sacrificial film with a high wet etching rate so as to obtain a wet etching selectivity with respect to a movable electrode when manufacturing a cantilever structure sensor. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) placing a substrate with a sacrificial film containing impurities on a substrate support in a process chamber, wherein the sacrificial film is formed so as to cover a control electrode, a pedestal and a counter electrode formed on the substrate; (b) heating the substrate; and (c) modifying the sacrificial film into a modified sacrificial film by supplying an oxygen-containing gas in a plasma state to the substrate to desorb the impurities from the sacrificial film after (b).

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer, a titanium nitride layer, a metal layer, and a first silicon nitride layer. At least one trench is recessed inward from a surface of the semiconductor substrate. The silicon oxide layer is formed on an inner wall of the at least one trench. The titanium nitride layer is formed on a portion of the silicon oxide layer away from the surface of the semiconductor substrate. The metal layer is filled in a portion of each of the at least one trench. The metal layer is selectively deposited on the titanium nitride layer and comprises a material selected from ruthenium and cobalt. The first silicon nitride layer is filled in a remaining portion of each of the at least one trench to contact the metal layer, and is surrounded by the silicon oxide layer.

Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

Abstract: There is provided a method of selectively patterning a device structure. A hollow shadow wall is formed on a substrate. The hollow shadow wall is formed of a base lying on a surface of the substrate, and one or more side walls connected to the base. The one or more side walls extend away from the surface of the substrate and around the base to define an internal cavity of the hollow shadow wall. A device structure supported by the substrate adjacent to the shadow wall is selectively patterned by using a deposition beam to selectively deposit a layer of deposition material on the device structure. The deposition beam has a non-zero angle of incidence relative to a normal to the surface of the substrate and an orientation in the plane of the substrate's surface, such that the shadow wall prevents deposition on a surface portion of the device structure within a shadow region defined by the shadow wall.

Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.

Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: A method and apparatus for use in a wafer processing are disclosed. In an embodiment a includes providing the wafer on a receptacle, wherein the receptacle comprises a light port, and wherein the light port includes a source of light, shining a light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer and processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.

Abstract: Methods of selectively depositing a film on a hydroxide terminated surface relative to a hydrogen terminated surface are described. The hydrogen terminated surface is exposed to a nitriding agent to form an amine terminated surface which is exposed to a blocking molecule to form a blocking layer on the surface. A film can then be selectively deposited on the hydroxide terminated surface.

Abstract: A semiconductor memory includes first to fourth regions that are arranged in a first direction, and first to third stacked bodies. An active region and a dummy region are provided in the first to third regions. The first stacked body includes an alternating stack of first insulators and first conductors in the active region. The second stacked body includes an alternating stack of second insulators and second conductors in the dummy region. The third stacked body includes an alternating stack of third insulators and third conductors. One of the third conductors closest to a substrate is electrically insulated from one of the first conductors closest to the substrate and electrically connected to one of the second conductors closest to the substrate.

Abstract: The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.

Abstract: A backside illuminated image sensor includes pixel regions disposed in a substrate, an insulating layer disposed on a frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, and an anti-reflective layer disposed on a backside surface of the substrate. The substrate has a first opening for partially exposing a backside surface of the bonding pad, the insulating layer has a second opening for partially exposing the backside surface of the bonding pad, and the anti-reflective layer has a first portion extending along an inner side surface of the first opening.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.