Patents Examined by Julia Slutsker
  • Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor
    Patent number: 11437594
    Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Timothy Vasen, Mark Van Dal, Gerben Doornbos, Matthias Passlack
  • Integrated circuit having a high cell density
    Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Confined work function material for gate-all around transistor devices
    Patent number: 11430660
    Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 30, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Choonghyun Lee, Takashi Ando, Alexander Reznicek, Pouya Hashemi
  • Methods for forming recesses in source/drain regions and devices formed thereof
    Patent number: 11417740
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yu-Lien Huang
  • Module, method for manufacturing module, and electronic device
    Patent number: 11417693
    Abstract: Provided is a module including an organic substrate, an image sensor mounted on an upper surface of the organic substrate, a wire connecting the image sensor and the organic substrate, and a wire sealing unit adhered to a side surface of the image sensor while encompassing the wire. A thermal conductivity of the wire sealing unit is higher than a thermal conductivity of the organic substrate.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: August 16, 2022
    Assignee: SONY CORPORATION
    Inventors: Hidetsugu Otani, Yuuji Kishigami
  • Semiconductor structure having memory device and method of forming the same
    Patent number: 11411011
    Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Yu-Ming Lin, Han-Jong Chia
  • Display apparatus including auxiliary pixels
    Patent number: 11404512
    Abstract: A display apparatus includes a substrate that includes a sensor area, a first non-display area at least partially surrounding the sensor area, and a display area at least partially surrounding the first non-display area. A plurality of auxiliary pixels is disposed in the sensor area. The plurality of auxiliary pixels is configured for passive matrix driving. A plurality of main pixels is disposed in the main display area and is configured for active matrix driving.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Changmok Kim, Dongwon Han
  • Semiconductor devices including a support pattern on a lower electrode structure
    Patent number: 11404266
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: August 2, 2022
    Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
  • Metal line patterning
    Patent number: 11404314
    Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Sony Varghese, M. Arif Zeeshan, Shantanu Kallakuri, Kelvin Chan
  • Semiconductor storage device and method of manufacturing the same
    Patent number: 11398494
    Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 26, 2022
    Assignee: Kioxia Corporation
    Inventors: Yuta Saito, Shinji Mori, Atsushi Takahashi, Toshiaki Yanase, Keiichi Sawa, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Semiconductor device and method for manufacturing the same
    Patent number: 11393917
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 19, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takahiro Tsuji, Kunihiko Suzuki
  • Semiconductor device
    Patent number: 11387345
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guk Il An, Keun Hwi Cho, Dae Won Ha, Seung Seok Ha
  • Plasma processing method
    Patent number: 11373875
    Abstract: There is provided a plasma processing method for forming shallow trench isolation (STI) on a silicon substrate, the plasma processing method including: a trench forming step of forming a trench in the silicon substrate by using plasma generated by pulse-modulated radio frequency power; and an oxidation step of oxidizing the silicon substrate by using only oxygen gas which is performed after the trench forming step, in which the trench forming step and the oxidizing step are repeated a plurality of times.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 28, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Yusuke Nagamitsu, Takeshi Shima, Takeshi Shimada, Hayato Watanabe
  • Capacitor structure and semiconductor structure
    Patent number: 11362169
    Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Kuang Kao
  • Method for inverse via patterning for back end of line dual damascene structures
    Patent number: 11361993
    Abstract: A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Katie Lutker-Lee
  • Display device
    Patent number: 11355738
    Abstract: A display device is provided, and includes a display panel, a multi-layered polarizer layer, and a cover layer. The multi-layered polarizer layer is disposed on the display panel. The cover layer is coated on the multi-layered polarizer layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 7, 2022
    Assignee: InnoLux Corporation
    Inventors: Yuan-Lin Wu, Kuan-Feng Lee, Jui-Jen Yueh
  • Non-volatile ferroelectric memory and method of preparing the same
    Patent number: 11348943
    Abstract: The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Fudan University
    Inventors: Anquan Jiang, Xiaojie Chai, Jianwei Lian, Jun Jiang, Menghan Ao
  • Image sensor packages formed using temporary protection layers and related methods
    Patent number: 11342369
    Abstract: An image sensor package may include a semiconductor wafer having a pixel array, a color filter array (CFA) formed over the pixel array, and one or more lenses formed over the CFA. A light block layer may couple over the semiconductor wafer around a perimeter of the lenses and an encapsulation layer may be coupled around the perimeter of the lenses and over the light block layer. The light block layer may form an opening providing access to the lenses. A mold compound layer may be coupled over the encapsulation layer and the light block layer. A temporary protection layer may be used to protect the one or more lenses from contamination during application of the mold compound and/or during processes occurring outside of a cleanroom environment.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: May 24, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Duane Kinsman, Swarnal Borthakur, Marc Allen Sulfridge, Scott Donald Churchwell, Brian Vaartstra
  • Display device having notched connection wiring
    Patent number: 11342405
    Abstract: A display device includes a substrate including a display region, a pad region spaced apart from the display region, and a bending region between the display region and the pad region. A plurality of pixel structures is positioned in the display region of the substrate. A plurality of pad wirings is positioned in the pad region of the substrate. A plurality of connection wirings electrically connect the pad wirings to the pixel structures. The connection wirings include a plurality of notches in the bending region.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Seil Cho
  • Semiconductor devices
    Patent number: 11342436
    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeho Hong, Yongseok Kim, Hyuncheol Kim, Seokhan Park, Satoru Yamada, Kyunghwan Lee