Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer, an unevenness-absorptive resin layer, and an adhesive resin layer in this order and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component such that the circuit forming surface is protected; and a step of forming an electromagnetic wave-shielding layer on the electronic component in a state of being attached to the adhesive laminated film.

Abstract: There is provided a processing method of a wafer having a functional layer on a front surface side. The processing method includes a laser processing step of forming laser processed grooves along streets while removing the functional layer along the streets by executing irradiation with a laser beam and a cut groove forming step of forming cut grooves inside the laser processed grooves along the streets by cutting the wafer by a cutting blade. The processing method also includes a grinding step of causing the cut grooves to be exposed on a back surface side of the wafer and dividing the wafer into plural device chips by grinding the back surface side of the wafer and thinning the wafer and a processing distortion removal step of supplying a gas in a plasma state to the back surface side of the wafer and removing processing distortion.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: A display device includes a base substrate, a plurality of display elements, a first light control layer, and a second light control layer. The base substrate includes a pixel region and a peripheral region adjacent to the pixel region. The display elements are disposed on the base substrate, overlap the pixel region in a plan view, and are configured to generate a first light. The first light control layer is disposed on the display elements, and includes a transmission part configured to transmit the first light, a first light conversion part configured to convert the first light into a second light, and a second light conversion part configured to convert the first light into a third light. The second light control layer overlaps at least a portion of the first light conversion part in the plan view and is configured to convert the first light into the second light.

Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

Abstract: A display apparatus is provided. The display apparatus includes a plurality of anode pads disposed on a substrate and spaced apart from each other along a first direction; a cathode pad disposed on the substrate and spaced apart from the plurality of anode pads along a second direction that crosses the first direction; a plurality of repair anode pads disposed on the substrate, spaced apart from each other along the first direction, and spaced apart from the plurality of anode pads and the cathode pad along the second direction; and a plurality of light emitting diodes (LEDs) disposed on the substrate and spaced apart from each other along the first direction, each of the plurality of LEDs including an anode that is electrically connected to a corresponding anode pad from among the plurality of anode pads and a cathode that is electrically connected to the cathode pad.

Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Abstract: A wafer has on one side a device area with a plurality of devices, partitioned by a plurality of division lines, and a peripheral marginal area formed around the device area. The device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The wafer is processed by providing a protective film, having a cushioning layer applied to a front surface thereof, attaching a front surface of the protective film, for covering the devices, wherein the protective film is adhered to at least the peripheral marginal area with an adhesive, and attaching a back surface of the protective film opposite to the front surface thereof to the cushioning layer. The protrusions are embedded in the cushioning. The side of the wafer opposite to the one side is ground for adjusting the wafer thickness.

Abstract: A packaged semiconductor device includes a lead frame and a semiconductor device. A solder joint is coupled between the lead frame and a terminal on the semiconductor device. A reflow wall is on a portion of the lead frame and is in contact with the solder joint. A molding compound covers portions of the semiconductor device, the lead frame, the solder joint, and the reflow wall.

Abstract: A light emitting device includes a substrate, a plurality of light sources, a light reflecting member and a resin member. The substrate defines a through hole. The light reflecting member includes a wall part having a first surface and a second surface. The first surface defines a plurality of surrounding parts respectively surrounding each of the light sources individually or two or more of the light sources in groups. The second surface defines a hollow part. The resin member is disposed inside the hollow part. The hollow part defines a first opening on a substrate side of the wall part. The through hole defines a second opening positioned inner than the first opening. The resin member is continuously in contact with the second surface and the upper surface of the substrate in a region between a peripheral edge of the second opening and a peripheral edge of the first opening.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.

Abstract: A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.

Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

Abstract: Provided are an organic electric element, a display panel and a display device including the organic electric element. The organic electric element includes a specific compound and satisfies a specific general formula related to energy levels of the component compounds so that they can have excellent efficiency or lifespan.

Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.

Abstract: A die-bonding method and a spraying device for an LED include: providing a substrate provided with a pad and a white oil layer covering wiring, placing a steel mesh on the substrate, and then spraying suspension containing solder paste on the pad by the spraying device, to form a solder paste film layer. Finally, a reflow process for the solder is performed. The solder paste is prepared on the pad by spraying, so that a crystal wafer is prevented from being tilted or short-circuited due to pulling or dragging of the solder paste during the reflow process for the solder, thereby improving uneven brightness of the surface light source.

Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.

Abstract: A micro light-emitting diode (micro-LED) chip adapted to emit a red light or an infrared light is provided. The micro-LED chip includes a GaAs epitaxial structure layer, a first electrode, and a second electrode. The GaAs epitaxial structure layer includes an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, and an N-type window layer along a stacking direction. The first electrode electrically contacts the N-type contact layer. The second electrode electrically contacts the N-type window layer.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.