Abstract: A technique regarding film formation capable of forming a three-dimensional pattern successfully is provided. A film forming method for a processing target object is provided. The processing target object has a supporting base body and a processing target layer. The processing target layer is provided on a main surface of the supporting base body and includes protrusion regions. Each protrusion region is extended upwards from the main surface, and an end surface of each protrusion region is exposed when viewed from above the main surface. The film forming method includes a first process of forming a film on the end surface of each protrusion region; and a second process of selectively exposing one or more end surfaces by anisotropically etching the film formed through the first process.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

Abstract: Disclosed in the present application are a quantum dot LED, a manufacturing method thereof, and a display device, belonging to the technical field of LED light sources. The quantum dot LED includes an LED support, an LED chip, a filling layer, and a quantum dot layer, where the LED support comprises a chamber; the LED chip is arranged on a bottom surface of the chamber; the filling layer covers the bottom surface of the chamber and the LED chip, and is engaged with walls of the chamber; and the quantum dot layer is arranged at an opening on a top surface of the chamber, a light incident side of the quantum dot layer abuts against a surface of the filling layer away from the bottom surface of the chamber, and a shortest distance h between the LED chip and the quantum dot layer meets h?0.03 mm.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material.

Abstract: A semiconductor device having high on-state current and high reliability is provided. The semiconductor device includes, a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor and a second conductor over the second oxide; a third oxide over the second oxide; a second insulator over the third oxide; a third conductor located over the second insulator and overlapping with the third oxide; a third insulator in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; a fourth insulator over the third insulator; a fifth insulator over the fourth insulator; and a sixth insulator over the third conductor, the second insulator, the third oxide and the fifth insulator.

Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.

Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ?3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.

Abstract: The present application discloses a semiconductor device with a tapering impurity region and the method for fabricating the semiconductor device with the tapering impurity region. The semiconductor device includes a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile.

Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

Abstract: An organic light-emitting display apparatus and a manufacturing method thereof have improved process stability and reliability by reducing damage to the organic light-emitting display apparatus during a manufacturing process. The organic light-emitting display apparatus includes: a substrate, a plurality of pixel electrodes, a pixel defining film, a plurality of hole control layers respectively arranged on the pixel electrodes, a plurality of emission layers respectively arranged on the hole control layers, a plurality of buffer layers respectively arranged on the emission layers, each of the buffer layers having a highest occupied molecular orbital (HOMO) energy level greater than the HOMO energy level of each of the plurality of emission layers, and an opposite electrode integrally provided over the buffer layers.

Abstract: A method of manufacturing a semiconductor device includes forming a spin on carbon layer comprising a spin on carbon composition over a semiconductor substrate. The spin on carbon layer is first heated at a first temperature to partially crosslink the spin on carbon layer. The spin on carbon layer is second heated at a second temperature to further crosslink the spin on carbon layer. An overlayer is formed over the spin on carbon layer. The second temperature is higher than the first temperature.

Abstract: There is provided a technique having a process that includes forming a film, which contains a first element and a second element on a substrate by performing a cycle a predetermined number of times, the cycle sequentially performing: (a) supplying a first precursor gas containing the first element to the substrate in a process chamber; (b) supplying a second precursor gas, which contains the first element and has a pyrolysis temperature lower than a pyrolysis temperature of the first precursor gas, to the substrate; and (c) supplying a reaction gas, which contains the second element that is different from the first element, to the substrate.

Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.