Abstract: A magnetic memory device has a plurality of write lines and a plurality of memory cells. Each of the plurality of memory cells are operatively positioned between a corresponding pair of the plurality of write lines. Each of the plurality of memory cells has a sense layer and a reference layer separated by an insulating layer. The reference layer of each of the plurality of memory cells includes a high coercivity permanent magnet.

Abstract: A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (VDIFF) to a selected memory cell by providing a column line potential (VC) and a row line potential (VR). According to this method, VDIFF is increased by an increment less than a transistor threshold voltage (VT). It is then determined whether the increased VDIFF results in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying VDIFF and increasing VDIFF by an increment more than VT to set the selected memory cell to a one state.

Abstract: The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer) read command; outputting the predetermined data to common I/O 30 and holding new data from memory array 12 upon (m+1)-th read command; holding predetermined data from common I/O 30 upon n-th (n is integer) write command; and storing the predetermined data in memory array 12 and holding new data from common I/O 30 upon (n+1)-th write command.

Abstract: A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

Abstract: A nonvolatile semiconductor memory device has a plurality of memory cells arranged in first and second directions, each of the memory cells having two MONOS memory cells controlled by one word gate and two control gates. A memory cell array region has a plurality of control gate lines formed by connecting, in the first direction, control gates of the memory cells in each column arranged in the first direction, and sub control gate lines extending in the first direction in an upper layer of the plurality of control gate lines, the number of the sub control gate lines being half the number of the control gate lines. Each two control gate lines adjacent across the boundaries between the plurality of memory cells in the second direction are connected in common with one sub control gate line.

Abstract: A method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell, wherein the source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.

Abstract: A non-volatile semiconductor memory device has a memory cell array region in which a plurality of memory cells are disposed in both a column direction and a row direction, each of the memory cells having first and second MONOS memory cells that are controlled by a word gate and first and second control gates. The memory cell array region is divided in the row direction into a plurality of sector regions 0 extending longitudinally in the column direction. Each of the sector regions has a plurality of memory cells disposed in each of columns arrayed in the column direction. A control gate drive section has a plurality of control gate drivers for each of the sector regions. Each of the control gate drivers sets a potential for the first and second control gates within the corresponding sector region, independently of the other sector regions.

Abstract: A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: A flash electrically-erasable, programmable read-only memory (EEPROM) has multiple source lines and source line select transistors. Each group of memory cells in the EEPROM is associated with one of the source line select transistors. Each source line is associated with more than one group of memory cells. When one group of memory cells is to be programmed, a relatively high voltage is coupled to its corresponding source line. Its corresponding source line select transistor then couples the source line to the group of memory cells to be programmed. In this manner, only the group to be programmed is exposed to the high voltage. This decreases the amount of high voltage stress placed on the other memory cells and increases the reliability and lifetime of the EEPROM.

Abstract: A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.

Abstract: A memory device includes an array of memory elements overlying a plurality of driver cells. Vias through an insulating layer connect the driver cells to the memory elements. The vias are distributed over the area of the array to connect the individual driver cells to the respective row and and/or column conductors of the memory array.

Abstract: Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

Abstract: A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

Abstract: A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.

Abstract: A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.

Abstract: A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one array plane while the write path writes in another array plane and one or more blocks are being erased. The uniform block size permits a symmetric layout and provides maximum flexibility in storage of data, code, and parameters. The uniform block size also allows spare blocks in the array planes to replace of any defective blocks. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution to replace addresses corresponding to defective memory elements. To reduce access delays, part of the input address such as the row address goes directly to decoders, while another part of the input address such as the block address goes to the CAM array.

Abstract: A diffusion replica delay circuit is included in a device with a device capacitance and operational characteristics. A diffusion replica capacitor, coupled to the device is capable of storing a predetermined replica charge representative of a selected device operational characteristic, and a diffusion replica transistor is coupled with the diffusion replica capacitor, and is coupled between the diffusion replica capacitor and a charge sink. The transistor is disposed to control the magnitude of the predetermined replica charge.

Abstract: A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.

Abstract: An address selection circuit and method selects an internal address from a plurality of input address signals and avoids unnecessary signal transitions to reduce current consumption. A latch coupled to the outputs of first and second transfer gates latches either the first or second of the respective input address signals as the internal address and maintains the logic level of the input address signal even after enable signals for each of the transfer gates becomes inactive to prevent unnecessary transitions in the internal address.