Abstract: In the operation cycle, memory chip 200 initiates a refresh operation in synchronism with an external clock signal CLK after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of a clock signal CLK.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group of address elements is greater than current-carrying capability of the second group of address elements. Current flowing through the address elements during programming causes the resistance states of only the second group of address elements to change.

Abstract: A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.

Abstract: A method and apparatus for determining the write-recovery of an embedded memory by performing successive pseudo-write operations followed by read operations until a “just-valid” result is achieved. The read operations may include addressing memory cells storing a logic value opposite that of memory cells coupled to the bit lines in the pseudo-write operations.

Abstract: The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is reduced such that a compact field concentration is attained, for example, by the use of ferrite in the area around the magnetic memory cells.

Abstract: The presents invention provides an initialization method of a P-type silicon nitride read only memory. A P-type silicon nitride read only memory is provided. An ultra-violet light is uniformly radiated onto the P-type silicon nitride read only memory. Electron traps are thus evenly distributed in a silicon nitride layer of the P-type silicon nitride read only memory. The P-type silicon nitride read only memory is thus uniformly programmed to a low threshold voltage (Low|Vt|) to achieve the device initialization effect.

Abstract: A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (RL) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of the one-way buffer propagates through the Josephson transmission line to generate a double flux quantum pulse at the transmission line output.

Abstract: A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Abstract: An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

Abstract: A semiconductor memory device includes a plurality of memory cells each having, alternately provided in a word line direction, an active region (channel forming region) comprised of a first conductivity type semiconductor and impurity regions comprised of a second conductivity type semiconductor shared by adjacent memory cells. One embodiment of the method comprises driving control gates capacitively coupled with the borders of the active regions with impurity regions and electrically isolated from the word lines to electrically divide the physical memory cell array into n number of memory cell arrays, and driving the impurity regions and word lines in the same memory cell array to operate in parallel the plurality of memory cells connected to the same word line out of the cell columns.

Abstract: A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

Abstract: A high speed data path includes a first plurality of inverters skewed toward one logic level alternating with a second plurality of inverters skewed toward a second logic level. As a result, the inverters in the first plurality accelerate one transition of a digital signal and the inverters in the second plurality accelerate the opposite transition of the digital signal. Prior to applying the digital signal to the inverters, the inverters are preset to a logic level from which they will transition in an accelerated manner. As a result, a transition of the digital signal is coupled through the inverters in an accelerated manner.

Abstract: A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit, for the CAS latency of no less than two, stores read data in response to the second clock signal attaining the active state, and for the CAS latency of one, stores read data in response to the first clock signal and an equalization signal each attaining the active state.

Abstract: An internal voltage from an internal voltage generating circuit is transmitted to a pad in accordance with a control signal, and a buffer circuit coupled to the pad is set in an inactive state. The pad is connected to an external pin terminal via a bonding wire. Consequently, a semiconductor integrated circuit capable of monitoring and forcedly setting an internal voltage from an outside of the circuit device is realized with a minimum number of pin terminals without increasing the number of external pin terminals.

Abstract: A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.

Abstract: A method for preventing electromigration in a magnetic random access memory (MRAM) is described. In the method, after a programming step, a signal which compensates for the electromigration and has opposite polarity is fed to the wordline and bitline in such a way that programming does not occur in the memory cells.

Abstract: A memory includes firs circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bLs coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cell in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.