Abstract: A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract: The present invention discloses a method, an apparatus, and a system for adaptively adjusting a voltage. The method includes: acquiring an internal temperature code of a system chip and a time sequence code of a system logic circuit, where the internal temperature code is detected by a temperature sensor and the time sequence code is output by a time sequence monitoring unit; selecting a time sequence reference calibration code from multiple configured time sequence reference calibration codes according to the acquired temperature code; and comparing the acquired time sequence code with the selected time sequence reference calibration code and determining, according to a comparison result, an adjustment voltage to be output for a system load. By using the foregoing method, the present invention can better reduce a power loss and achieve a better power reduction effect.

Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: A semiconductor integrated circuit includes a first internal voltage generator including a PMOS and a first comparator, and a second internal voltage generator including an NMOS, a second comparator, and a voltage pump generator configured to provide a pumping power voltage to the second comparator. A power control circuit switchably enables an output from the first internal voltage generator during a power-on of the semiconductor integrated circuit and enables an output from the second internal voltage generator after the power-on.

Abstract: A current providing circuit, for providing an output current at an output terminal, comprising: a current providing module, coupled to a first predetermined voltage level, for providing the output current according to the first predetermined voltage level and a control voltage transmitted to the current providing module; and a control voltage generating module, for generating the control voltage corresponding to the first predetermined voltage level and a threshold voltage of the current providing module.

Abstract: A method and apparatus for an adjustable filter system comprises a first integrated circuit generating a reference value that represents a corner frequency of a filter within the first integrated circuit; sending the reference value that represents the corner frequency of the filter across an interface to a second integrated circuit; receiving, across the interface from the second integrated circuit, a filter adjustment value; and changing the corner frequency of the filter using the filter adjustment value to adjust a passband and a stopband of the filter. The apparatus and method also comprises a second integrated circuit detecting a filter adjustment event, wherein the filter adjustment event comprises receipt of the reference value; calculating the filter adjustment value to change a corner frequency of the filter within a first integrated circuit; and sending the filter adjustment value across the interface to the first integrated circuit.

Abstract: A regulating system for an insulated gate bipolar transistor (IGBT) includes a clamping circuit coupled to the IGBT. The IGBT is coupled to a gate driver circuit. The regulating system also includes a feedback channel coupled to the clamping circuit. The feedback channel is configured to transmit signals representative of a conduction state of said clamping circuit. The regulating system further includes at least one gate driver controller coupled to the feedback channel and the gate driver circuit. The gate drive controller is configured to regulate temporal periodicities of the IGBT in an on-condition and an off-condition.

Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.

Abstract: The present disclosure relates to an Apparatus comprising at least one resistive voltage divider and at least two inverters, wherein the resistive voltage divider is coupled between a first supply potential terminal (VDD) and a second supply potential terminal (VSS), wherein the voltage divider comprises a first resistor, a second resistor, a third resistor and a fourth resistor being serially connected, and wherein a first connection point of the second resistor and the third resistor is connected to an voltage input, and a second connection point of the first resistor and the second resistor is connected to the input side of a first inverter, and a third connection point of the third resistor and the fourth resistor is connected to the input side of a second inverter, wherein the first inverter and the second inverter are configured to provide a first output voltage if a first voltage is applied to the voltage input, and the first inverter and the second inverter are configured to provide a second output vo

Abstract: In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section.

Abstract: According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract: A voltage generating apparatus is provided. The voltage generating apparatus includes a reference voltage generator and an output voltage generator. The reference voltage generator is used for generating a reference voltage, and the reference voltage generator decides to generate the reference voltage or not according to a control signal. The output voltage generator includes a comparator, a variable resistor and a current source. The comparator compares the reference voltage and an output voltage to generator a calibrating signal. A resistance of the variable resistor is decided by the calibrating signal. The current source provides an output current to flow through the variable resistor for generating the output voltage. Wherein, the reference voltage is generated during an initial timing period, and the generator is turned off after the initial timing period. The initial timing period is determined according to the control signal.