Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.

Abstract: Generator of clock pulses having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator controlled by a binary selection signal having a first and second logic level, in order to generate periodic pulses having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor triggered by the periodic pulses and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal and the periodic pulses, and generating the selection signal at a f

Abstract: A voltage circuit for a device having an active period and an inactive period comprises a reference voltage generator generating a reference voltage and a voltage stabilizer receiving the reference voltage. The voltage stabilizer includes first circuit componentry for raising a potential of an output terminal during the active period of the device and second circuit componentry for lowering a potential of the output terminal during at least the inactive period of the device.

Abstract: The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

Abstract: An integrated semiconductor circuit includes a semiconductor substrate. A number of first potential buses carry a first supply potential of the semiconductor circuit during operation. A number of second potential buses carry a second supply potential of the semiconductor circuit during operation. A number of circuit portions formed on the substrate are each connected between one of the first and one of the second potential buses for being supplied with electrical voltage. Connection points are formed on the substrate and are each assigned to one of the circuit portions for receiving an input or output signal for the circuit portion during operation of the circuit portion. Protective circuits are formed on the substrate and are each assigned to one of the circuit portions for preventing overvoltage. The protective circuits each have an input side connected to one of the connection points and an output side connected to the circuit portion.

Abstract: A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

Abstract: The switch of this invention has two conduction terminals and basically consists of the parallel coupling, across the two conduction terminals, of a first N-channel MOS transistor and second P-channel MOS transistor. The first MOS transistor will be conducting when the signal applied to the conduction terminals has a first polarity, and the second MOS transistor will be conducting when the signal applied to the conduction terminals has a second polarity. Advantageously, if two unidirectional conduction circuit elements are respectively connected in series with the main conduction paths of the two MOS transistors, the drain/body junctions of the latter will never be conducting regardless of the way the switch is connected.

Abstract: A charge pump voltage booster circuit with control feedback of the type comprising an output line connected to a load and on which is produced an output voltage boosted in relation to a supply voltage and a feedback loop incorporating a charge pump connected to said line and a control logic circuit of said pump interlocked with a comparator having an input connected to the line comprises also an auxiliary charge pump connected in turn to said line and designed to supply a quantity of current greater than or equal to the leakage currents of the load in stand-by condition. The auxiliary pump has current consumption much lower than that of the main charge pump. In addition, upon emerging from the off state there is provided starting of the main charge pump for a brief time period sufficient to take the booster output to a sufficient value.

Abstract: A pulse signal shaper supplying a pulse signal having a stable pulse width, including an input circuit that produces a first pulse signal in response to an input signal, a delay circuit that produces a second pulse signal obtained by delaying the first pulse signal by a predetermined time, and a signal mixing circuit that is connected to the input circuit and the delay circuit. The mixing circuit combines the first pulse signal and the second pulse signal to produce a third pulse signal having a pulse width equal to or greater than a delay time provided by the delay circuit, and supplies the third pulse signal as an output signal from the pulse signal shaper. In a preferred embodiment, the input circuit includes an oscillator responsive to the input signal. When the input signal has a higher frequency than a predetermined frequency, the input signal is supplied as the first pulse signal at a frequency equal to te frequency of the input signal.

Abstract: An open-loop biasing circuit for a magnetoresistive element provides high common mode and power supply rejection. Two current sources are connected together by two conduction paths. A first conduction path has two impedances. One impedance is tied between the first current source and ground and the second impedance is tied between the second current source and ground. The second conduction path includes the magnetoresistive element. A capacitive path between the two current sources reduces power supply noise and a voltage follower reduces parasitic capacitance in the capacitive path.

Abstract: A FET band-gap reference generating circuit having a two-branch differential amplifier with a saturation state FETs for equal branch current, independent of power supply voltage, with a feedback connection to a reference FET in one branch, for driving the steady state output to the threshold voltage of the reference FET, also independent of the power supply voltage. A multistage circuit connects a divided down output of a first FET band-gap reference generating circuit to a current bias terminal of similar second FET based differential amplifier so that the steady state output of the second amplifier is equal to the sum of the divided down output and a threshold voltage of a second reference FET in the second amplifier.

Abstract: A signal transfer circuit for enabling rapids transfer of differential electrical signals among multiple signal paths is provided. The circuit comprises first and second pairs of signal transfer terminals, a pair of internal nodes, first and second pairs of isolation devices, a differential signal amplifier, a gain-enhancing cross-coupled pair of devices, and a precharge circuit. The first and second pairs of isolation devices are of a single device type and are coupled between respective ones of the signal transfer terminal pairs and the internal node pair. The isolation devices each have a control terminal for receiving an isolation control signal. The differential signal amplifier circuit is coupled to the internal nodes, and is comprised of complementary device types. The amplifier circuit has a control terminal for receiving an amplifier control signal for enabling the amplifier circuit.

Abstract: A bus to which a bus control circuit and at least one electronic circuit are connected is controlled by a) storing a signal level which is output to the bus when the bus is in an active state, and b) fixing the bus to the signal level stored in the step a) when the bus switches to an inactive state.

Abstract: The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level.

Abstract: The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.

Abstract: A circuit for supplying a reference level to a differential sense amplifier in a semiconductor memory circuit, includes a first circuit for detecting an external power supply voltage, and a second circuit controlled by the first circuit, for controlling a reference level to be supplied to a sense amplifier, on the basis of the result of the detection of the external power supply voltage. Regardless of whether the external power supply voltage is a first power supply voltage (5 V) or a second power supply voltage (3 V), it is possible to output the reference level which can avoid occurrence of malfunction.

Abstract: An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.cc in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device.

Abstract: Activatable/deactivatable circuit arrangement for producing an output reference voltage having a first transistor (T1) whose emitter is connected with a reference potential (M) and whose base and collector are connected with one another, having a second transistor (T2) whose base is connected with the base of the first transistor (T1), having a first resistor (R1) that is connected between the collector of the first transistor (T1) and an output terminal (U) for supplying the output reference voltage, having a second resistor (R2) that is connected between the collector of the second transistor (T2) and the output terminal (U), having a third resistor (R3) that is connected between the emitter of the second transistor (T2) and the reference potential (M), having a third transistor (T3) whose base is connected with the collector of the second transistor (T2) and whose emitter is connected with the reference potential (M), and having a controlled current source (T4) that is connected between a supply potential

Abstract: An integrated voltage/current reference having substantially reduced temperature and voltage coefficient with simultaneous nanowatt power consumption includes a nanopower voltage/current reference topology having a substantial temperature coefficient and minimal voltage coefficient and augmented with a floating voltage proportional to absolute temperature (PTAT) within a feedback loop to compensate for differentials in .beta. exponential temperature dependencies of N-Channel and P-Channel MOS devices used within commonly available semiconductor processes. The resulting reference supplies both voltage as well as current references which have greatly reduced temperature coefficients. In addition, the resulting circuit topology generates a voltage reference which has a parabolic temperature coefficient similar to that produced by a conventional bandgap reference.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1,/.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.