Abstract: A first FET is connected between first and third nodes, a second FET is connected between second and fourth nodes, a third FET is connected between third and fifth nodes and a fourth FET is connected between fourth and fifth nodes. A fifth FET is connected between first and sixth nodes and a sixth FET is connected between second and sixth nodes. The gates of the first, fourth and sixth FETs are connected to a first control terminal and the gates of the second, third and fifth FETs are connected to a second control terminal. A power-supply terminal is connected to the fifth and sixth nodes. The first and second nodes are connected to a common terminal through first and second capacitors, respectively. The fifth and sixth FETs form a pull-up switching circuit. The pull-up switching circuit pulls up the source of an FET in an OFF state to the power-supply voltage and isolates the source of an FET in an ON state from the power-supply voltage.

Abstract: A current source apparatus with bias switches, applied in digital-to-analog converters, is disclosed. The current compliance and settling time performances can be promoted via improving the structure of the bias circuit and making the MOS transistors operate in the saturation region, without increasing the dimensions of the MOS transistors.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.

Abstract: The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree.

Abstract: A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.

Abstract: An MOS transistor current source has a current mirror constructed of an MOS transistor pair with the transistors having intentionally mismatched W/L aspect ratios such that the intentionally mismatched transistor pair develops a mirror current that varies in an inversely proportional fashion to the process. A precision reference current drives a first, short channel device of the pair which develops a bias voltage which is coupled to the gate terminal of a second, long channel device of the pair. The long channel device conducts a current in operative response to the bias voltage, which current will increase or decrease a corresponding amount in an inversely proportional relationship to the drive strength of the short channel device.

Abstract: In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors.

Abstract: An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to a frequency lower than that of the input signal and one tuned to a frequency higher than that of the input signal. The loaded outputs are recombined in a vector summing network to synthesize the required phase shifted output signal. This technique permits implementation on a monolithic integrated circuit (MIC) with high gain at high frequencies (e.g. 10 GHz). It also allows a large dynamic range of operation and a large (i.e., greater than 90 degrees) controllable phase shift. This is accomplished without the use of variable reactance elements or any other components external to the MIC.

Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Abstract: The present invention comprises a noise insensitive current source circuit having a high power supply rejection ratio. The circuit of the present invention is for use with noise sensitive circuits. The circuit of the present invention includes a first reference current source, a second reference current source, and a first, second, third, and fourth transistor. The first transistor has a drain coupled to a power supply and a source coupled to a ground via the first reference current. The second transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the second transistor is coupled to the gate of the first transistor and to the source of the first transistor. A third transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the third transistor is coupled to the source of the second transistor.

Abstract: A device for comparing two DC voltages (U.sub.1, U.sub.2) comprises a voltage comparator (3) having two inputs (9, 11). One of the two voltages (U.sub.1, U.sub.2) to be compared to each other is fed directly into one of the inputs (9, 11). The other voltage enters a voltage-conversion device (2) in which the voltage to be compared is superimposed with the DC voltage (8) so that a DC voltage arises at the output (7) of the voltage-conversion device (2), which voltage periodically fluctuates back and forth between an upper and a lower amplitude value in the cycle of the square-wave signal (8). The distance between the two amplitude values corresponds to the tolerance band within which the two voltages (U.sub.1, U.sub.2) to be compared with one another must be identical.

Abstract: A high voltage generating circuit which provides a constant V.sub.PP output without any threshold voltage drop and which does not suffer from latch-up problems is described. Thus a voltage boosting circuit which provides for a boosted voltage V.sub.PP at an output node, from a supply voltage V.sub.DD, includes a precharge transistor element responsive to a precharge clock signal for transferring the supply voltage V.sub.DD to a boost node for precharging the boost node to the full supply voltage V.sub.DD. The circuit further includes a capacitive element connected between the boost node and a pump node, the capacitive element pumping the boost node in response to a pump voltage signal applied to the pump node; and a switching element connected between the boost node and the output node, for transferring charge from the capacitive element to the output node to provide the boosted voltage V.sub.PP. In particular the precharge transistor element is an PMOS transistor.

Abstract: A novel waveform generating for generating a waveform having symmetrical rise and fall times. The waveform generator of the present invention includes a first current source, a second current source, a MOS capacitor and a clamping circuit. The first current source and the second current source are coupled to a node such that current generated by the first current source flows into the capacitor and current generated by the second current source flows out of the capacitor. The clamping circuit is also coupled to the node such that the output voltage generated by the waveform generator is limited to a minimum and a maximum value. Therefore, by controlling the current flowing into the node, and the capacitance at the node, the rate at which the output voltage changes over time is controlled. As such, a waveform having very precise rise and fall times is generated.

Abstract: A power applying circuit for an internal logic circuit includes a plurality of basic power applying units coupled to the internal logic circuit in parallel, each of the basic power applying units including a logic gate unit outputting a pulse in response to two input signals having a time interval with respect to each other, and a transmission gate coupled to the logic gate unit and receiving the pulse.

Abstract: Briefly, in accordance with one embodiment of the invention, a bootstrap circuit comprises a pair of drivers coupled together so as to form a bootstrap node and a bipolar transistor coupled to the bootstrap node. A method of using a bipolar transistor in such a bootstrap circuit comprises the step of applying a voltage signal to the input ports of the drivers, the voltage signal having a magnitude sufficient to activate the bipolar transistor.

Abstract: A switch mode voltage regulator with synchronous rectification that produces ripple cancellation with fast load response is described. The switch mode voltage regulator comprises a main step-down regulator with synchronous rectification with an auxiliary step-down regulator that produces an output ripple cancellation current that is equal but opposite to the output ripple of the main regulator during static load conditions. During changing load conditions a feedback control circuit changes the duty cycle of the main regulator while a time-delay circuit prevents a change of the duty cycle in the auxiliary regulator. Thus, the main regulator is allowed to change its average current while preventing a counteracting average current change in the auxiliary regulator. An embodiment is described in which the duty cycle in the auxiliary regulator is changed in phase with the duty cycle of main regulator to further improve the dynamic response to load changes.

Abstract: A mode setting circuit for a semiconductor memory device reduces power consumption and layout area by utilizing a complimentary pair of transistors to sense the state of a fuse. The fuse and complimentary pair of transistors are coupled in series between a power supply and ground. The gates of the transistors are coupled together to receive an input signal. An output signal is generated at a node between the pair of transistors. A latch is coupled to the node to latch the output signal. When the fuse is intact, the circuit generates the output signal responsive to the input signal. When the fuse is blown, the circuit maintains the output signal in a steady state.

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. The plurality of MOSFETs preferably includes at least one MOSFET having a first conductivity type and at least one MOSFET having a second conductivity type. Each MOSFET has an initial threshold voltage. The integrated circuit also preferably includes first and second biasing circuits which selectively bias only a selected well a corresponding conductivity type of the plurality of MOSFETs to produce an absolute value of an effective threshold voltage of only the selected MOSFET which is lower than an absolute value of the initial threshold voltage thereof and thereby inhibit a high standby current for the integrated circuit. Method aspects of the invention are also disclosed.

Abstract: By setting the substrate potential of a transistor of a driver means lower than the substrate potential of a transistor of a bias means in an intermediate potential generation circuit which supplies a cell plate potential of a memory cell and a precharge potential of a bit line, a flow of a through current in a transistor of the driver means is prevented. Therefore, reduction of a power consumption of the device during standby can be realized.