Abstract: An output circuit for producing 5 volt output signals from a chip that is manufactured in a 3 volt process, is provided with a control signal logic circuit, a pseudoground generating circuit, and an output signal generation circuit. The control signal logic circuit receives 3 volt data signals from the internal logic circuitry of the chip, and produces control signals as a function of these 3 volt data signals. The pseudoground generating circuit is coupled to the control signal logic circuit and generates a pseudoground greater than zero volts and intermediate output signals as a function of the control signals produced by the control signal logic circuit. The output signal generation circuit is coupled to the pseudoground generating circuit and generates the 5 volt output signals as a function of the intermediate output signals generated by the pseudoground generating circuit.

Abstract: A low power line driver uses a dynamic biasing scheme together with single ended architecture to achieve low power, fast speed and high return loss. The line driver includes a first and second operation amplifier each having an output port for generating an output pulse signal having a rising and falling edge. The load is coupled to the first and second output port by a transformer. A first and second digital control circuit is coupled to the first and second operational amplifiers to control the operational amplifiers. The first and second operational amplifiers further include a pulse circuit for generating the output pulse signal and a selectable current source having a first mode for injecting a high current to the pulse circuit to provide a high slew rate for the rising edge of the output pulse signal and a second mode for injecting a second current to the pulse circuit during the generation of the remaining portion of the output pulse signal.

Abstract: A structure is provided to create a voltage-independent capacitive structure using a typical MOS fabrication process. The capacitive structure includes two FET devices connected in series by having their source, drain, and body terminals all coupled together into a common node. A biasing circuit that includes a current generator and a current mirror biases the common node so that a constant capacitance is maintained across the gate terminals of the two serially connected FET devices, independent of the applied voltage.

Abstract: A power supply noise eliminating method eliminates power supply noise in a semiconductor integrated circuit having a plurality of first terminals coupled to a first power supply voltage and one or a plurality of second terminals coupled to a second power supply voltage which is different from the first power supply voltage. The power supply noise eliminating method includes the steps of (a) supplying the first power supply voltage to one of the first terminals, and (b) supplying the second power supply voltage to another one of the first terminals via an impedance circuit, thereby eliminating the power supply noise with respect to at least the first power supply voltage.

Abstract: An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.

Abstract: In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small signal differential pulses which swing a differential pair of transistors by a small amount. This is done with level converters. The differential pair is kept in a saturation region, so that a large swing is not needed from the level converters and channel creation/destruction noise is avoided in addition to the noise reduction due to smaller swings. To avoid inherent offsets which might require a nonzero delta time width difference in the input pulses to produce a zero delta current, identical differential structures are used at the inputs for the two input pulse signals.

Abstract: An improved current mode driver circuit uses N-type transistors in current mirrors to achieve higher speed operation at lower cost. A pair of matched low frequency P-type transistors provide a small amount of current to each side of the differential amplifier which comprise of only N-type transistors in a current mirror connection to amplify the current supplied thereto.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: An amplifier circuit has an amplifying transistor which is switched on and off by a switching transistor under control of a control signal selectively applied to the switching transistor. In this way a selection is made whether or not to amplify an input signal on an antenna. The switching transistor forms part of the biasing circuit for the amplifying transistor such that when the switching transistor is on the amplifying transistor is biased off. A PIN diode and series resistor are together connected in shunt across the switching transistor such that the bias voltage which causes the amplifying transistor to be off causes the PIN diode to be forward biased thereby causing the antenna to be terminated with the resistor the value of which may be chosen to be 50 ohms.

Abstract: A semiconductor integrated circuit device includes a flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage, and a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage. A switching unit selects either the flat-range voltage or the burn-in voltage, a selected voltage being supplied to an internal circuit. A switching instruction unit includes switches and generates a switching instruction signal by an ON/OFF control of the switches. A switching control unit controls the switching unit in accordance with the switching instruction signal.

Abstract: A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude.

Abstract: The invention provides a method and system for reshaping periodic waveforms to a selected duty cycle. An incoming periodic waveform has its edge transitions stretched out, and the stretched edge transitions compared with an adaptively selected threshold, to generate a reshaped waveform with a 50% duty cycle. The incoming periodic waveform is a square wave clock signal. The edge transitions are stretched using an inverter which is biased and filtered, and the stretched edge transitions are squared off using a comparator. The reference voltage for the comparator is selected using a second filter coupled in a feedback configuration with the biasing transistors for the inverter.

Abstract: An interface allowing to transfer serial test data from a Test Access Port (TAP) to controllers located in several clock domains is described. The clock frequencies can be different from each other and do not need to be related in phase to each other or with the clock of the TAP. The interface is proven to work reliably as long as the clock frequencies used for the test controllers and registers is 3 times higher than the one of the TAP used to source the serial test data.

Abstract: A highly efficient compact multiple output voltage generation circuit is designed for use in integrated circuit devices such as DRAMs which require multiple internal voltage supplies for optimum performance. An oscillator is connected to a primary coil of a microtransformer. The microtransformer secondary coil has multiple taps one of which is connected to ground. A second transformer tap is connected to a transformer output node. The oscillating transformer output signal is capacitively coupled to a voltage rectifier. The input to the rectifier is biased to one diode drop below Vcc. The output of the rectifier is an internal supply voltage greater than ground. Another transformer tap is connected to a negative oscillation output node. The negative oscillating signal is rectified to produce a negative internal supply voltage. The voltage generation circuit operates effectively at low Vcc input levels where capacitor based voltage pumps often fail. The circuit is compatible with CMOS manufacturing processes.

Abstract: A precision bandgap reference circuit which uses an operational amplifier that has the positive and negative input terminals connected to a diode/resistor combination and a diode respectively. The output of the operational amplifier drives a diode connected PMOS transistor which regulates current sources which drives into the diode/resistor combination and the diode inputs to the operational amplifier. This allows the operational amplifier to have enough gain to minimize errors across the diode/resistor combination and the diode inputs to the operational amplifier. This also allows an output stage driven by the operational amplifier to be biased with a Proportional To Absolute Temperature (PTAT) current which is well controlled.

Abstract: This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.

Abstract: A controlled output voltage is provided for a switching mode power converter operating in the continuous conduction mode without requiring a feedback path coupled to monitor the output voltage. Instead, a voltage related to the input voltage is monitored. The monitored voltage is compared to a periodic waveform for forming a switch control signal. In the case of a buck converter operating as a voltage regulator, over each period of the periodic waveform, the periodic waveform is representative of the inverse function. In the case of a boost converter operating as a voltage regulator or buck converter operating as a bus terminator or power amplifier, over each period of the periodic waveform, the periodic waveform has a linear slope. The switch control signal controls a duty cycle of the power switches. Therefore, switching is controlled in an open loop, rather than in a closed loop.

Abstract: A method and circuit (10) for limiting current (I.sub.COIL) in a load (16). The current limiting circuit (10) includes a sensing circuit (12) having a current indicator output terminal (20) connected to an inverting input of a comparator (11). A reference voltage node (24) of a reference voltage generator (13) is connected to the non-inverting input of the comparator (11). The comparator (11) generates an output signal in accordance with the current flowing in the load (16). If an overcurrent condition exists, the signal from the comparator (11) disables a control circuit (14) which turns off the sensing circuit (12). With the control circuit (14) disabled and sensing circuit (14) off, the current (I.sub.COIL) is prevented from flowing through the load (16).

Abstract: The invention relates to a device for setting at stand-by a bias source through a stand-by control signal, including an inverter with an active load controlled by the bias source. The inverter includes a first p-channel MOS transistor, whose source is connected to a positive terminal of the supply voltage of the bias source, whose drain constitutes the inverter output connected to a control input of the bias source, and whose gate constitutes the input of the inverter receiving the stand-by inducing control signal.

Abstract: A high-speed/high-slew-rate tri-modal all bipolar buffer/switch includes a unity-gain amplifier, a voltage source, and a maximum level detector and a minimum level detector adjusting a current source to sink or source current as required to quickly make the output voltage of the switch equal to the input voltage of the switch. The maximum level detector and the minimum level detector compare the output voltage to the input voltage. If the output voltage does not equal the input voltage, the current source acts as either a sink or source to make the output voltage equal the input voltage. In addition, the voltage switch holds a constant d.c. voltage at the output of the switch when the switch is powered down.