Patents Examined by Jung Kim
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Patent number: 12294364Abstract: A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.Type: GrantFiled: August 25, 2023Date of Patent: May 6, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Santosh Sharma, Mei Yu Soh
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Patent number: 12282589Abstract: An electronic device includes a power supply terminal, a voltage regulator connected to the power supply terminal, an electronic module connected to the voltage regulator, and a compensation circuit configured to receive an auxiliary current generated by the voltage regulator and being equal to a first fraction of the electronic module current. The compensation circuit includes a current source configured to supply a source current to a cold point, and a compensation stage connected to the power supply terminal and being traversed by an intermediate current equal to a difference between the source current and the auxiliary current and by a complementary current equal to the intermediate current multiplied by an inverse multiplication factor of the first fraction.Type: GrantFiled: February 10, 2023Date of Patent: April 22, 2025Assignee: STMicroelectronics (Rousset) SASInventor: Nicolas Demange
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Patent number: 12283960Abstract: A current-sink and method of using the same is provided for sinking transient load currents of a load coupled to a floating-rail. In one embodiment, the current-sink includes a latch system operable to receive a transient load current signal from the load and set a latch to apply a voltage to a gate of a current sinking switch. The current sinking switch includes a first source/drain (S/D) coupled to the floating-rail, and a second S/D coupled to ground, and is operable to sink the transient load current to provide a stable floating-rail voltage (VSSHV) on the floating-rail. Generally, the latch system further includes a dynamically biased comparator for comparing VSSHV to a reference voltage and resetting the latch when a difference is less than a predetermined voltage. A dynamic bias circuit coupled to a latch output enables the comparator only while the transient load current is present.Type: GrantFiled: April 26, 2023Date of Patent: April 22, 2025Assignee: Cypress Semiconductor CorporationInventor: Adrian Lin
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Patent number: 12283961Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.Type: GrantFiled: August 14, 2023Date of Patent: April 22, 2025Assignee: QUALCOMM IncorporatedInventors: Lalan Jee Mishra, Umesh Srikantiah, Richard Dominic Wietfeldt
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Patent number: 12283951Abstract: A voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage, a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage, a first PMOS transistor sourced with a first supply voltage, a second PMOS transistor sourced with the first supply voltage, and a voltage modulation circuit that is coupled between the first to second PMOS transistors and the first to second NMOS transistors, and is configured to provide a first intermediate signal based on the first and second control signals. The first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.Type: GrantFiled: February 16, 2023Date of Patent: April 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Yu Yu, Meng-Sheng Chang, Shao-Yu Chou
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Patent number: 12283945Abstract: A detection circuit is provided to output a feedback signal and a adjustment current when a voltage of a high-voltage side main terminal of a semiconductor switching device is equal to or higher than a preset threshold value in a period in which a gate drive circuit turns off the semiconductor switching device to cut off a current, a control circuit diagnoses a state of the semiconductor switching device or controls a signal to be outputted to the gate drive circuit, on the basis of the feedback signal, and a gate current, which is an output of the gate drive circuit, is adjusted by the adjustment current.Type: GrantFiled: February 17, 2021Date of Patent: April 22, 2025Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya Sakai, Kohei Onda
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Patent number: 12283958Abstract: A driver circuit for low voltage differential signaling, LVDS, includes a phase alignment circuit including an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and an output driver circuit coupled to the phase alignment circuit, the output driver circuit including a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal. The phase alignment circuit provides the inverted internal signal with its phase aligned to a phase of the internal signal.Type: GrantFiled: May 17, 2021Date of Patent: April 22, 2025Assignee: AMS-OSRAM AGInventors: Elisa Girani, Dominik Ruck
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Patent number: 12278627Abstract: A system includes multiple sensors and, for each sensor, a respective sensor controller of multiple sensor controllers. Each sensor controller is configured to implement a respective decimation filter that is configured to generate a single output value from multiple input samples generated by a corresponding sensor of the multiple sensors. The system further includes a master sensor controller of the multiple sensor controllers, which is configured to generate a sync signal upon receiving a threshold number of input samples. Each sensor controller other than the master sensor controller is configured to monitor sync signals generated by the master sensor controller and to provide an output value generated from input samples upon determining that the master sensor controller generated a sync signal.Type: GrantFiled: October 26, 2023Date of Patent: April 15, 2025Assignee: Google LLCInventor: Trevor Scott Bunker
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Patent number: 12278635Abstract: Embodiments relate to identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.Type: GrantFiled: August 25, 2023Date of Patent: April 15, 2025Assignee: APPLE INC.Inventors: Helena Deidre O'Shea, Ali Moaz, Tim Schoenauer, Rahmi Hezar
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Patent number: 12278566Abstract: A preprocessing circuit for a comparator has a high voltage selection circuit, a first constant voltage circuit, a second constant voltage circuit, a first transistor, and a second transistor. The high voltage selection circuit receives a first voltage and a second voltage, and provides a selected voltage. The first constant voltage circuit provides a first clamping voltage based on the selected voltage, and the second constant voltage circuit provides a second clamping voltage based on the selected voltage. The first transistor receives the first voltage and the first clamping voltage, and provides a first comparison voltage to a first comparison terminal of the comparator. The second transistor receives the second voltage and the second clamping voltage, and provides a second comparison voltage to a second comparison terminal of the comparator.Type: GrantFiled: February 24, 2023Date of Patent: April 15, 2025Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventor: Changxian Zhong
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Patent number: 12267067Abstract: A transceiver circuit includes a first interface and a second interface that are connected to an optical transceiver device, a receiver circuit, a transmitter circuit, and a compensation circuit. The receiver circuit includes a differential amplifier, where a first phase input terminal of the differential amplifier is coupled to the first interface, and a second phase input terminal of the differential amplifier is coupled to the second interface. The transmitter circuit includes a first transistor, where a terminal of the first transistor is coupled to the second phase input terminal, and another terminal of the first transistor is coupled to a ground terminal. The compensation circuit is configured to provide a leakage path for the first phase input terminal, or provide a compensation current for the second phase input terminal.Type: GrantFiled: October 24, 2023Date of Patent: April 1, 2025Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Furong Xiong, Kai Li, Wei Song
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Patent number: 12255658Abstract: Disclosed is a sub-sampling phase-locked loop circuit capable of avoiding harmonic locking, which comprises a harmonic suppression sampling charge pump module, a filter module and a voltage-controlled oscillator module; a reference clock signal and differential signals are respectively accessed to an input end of the harmonic suppression sampling charge pump module, an output signal of an output end of the harmonic suppression sampling charge pump module is accessed to a filter and then accessed to an input of a voltage-controlled oscillator, an output end of the voltage-controlled oscillator module outputs differential signals as the differential signals accessed to the input end of the harmonic suppression sampling charge pump module, output signals of the voltage-controlled oscillator module are used as final outputs of the phase-locked loop circuit, and the output differential signals are synchronous with the reference clock in phase at the same time.Type: GrantFiled: September 3, 2024Date of Patent: March 18, 2025Assignee: MAGNICHIP CO., LTDInventors: Hao Zhang, Chao Zhao
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Patent number: 12249992Abstract: A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.Type: GrantFiled: March 6, 2023Date of Patent: March 11, 2025Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Wenbo Tian, Chuan Gong, Zhijun Fan, Zuoxing Yang, Haifeng Guo
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Patent number: 12249989Abstract: A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.Type: GrantFiled: August 25, 2023Date of Patent: March 11, 2025Assignee: Realtek Semiconductor Corp.Inventor: Chia-Liang (Leon) Lin
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Patent number: 12244317Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.Type: GrantFiled: July 13, 2023Date of Patent: March 4, 2025Assignee: Faraday Technology Corp.Inventors: Vinod Kumar Jain, Mikhail Tamrazyan
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Patent number: 12244440Abstract: A communication apparatus includes a first substrate including a first transmission line, a metal portion functioning as a ground for the first substrate, spaced apart from the first transmission line, and a first termination circuit configured to terminate the first transmission line. The first substrate is fixed to any one of surfaces of the metal portion other than a surface where the first transmission line is disposed.Type: GrantFiled: March 1, 2023Date of Patent: March 4, 2025Assignee: Canon Kabushiki KaishaInventor: Masaru Tomabechi
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Patent number: 12244155Abstract: Systems configured to deliver wireless charging power to electronic devices and methods for delivering wireless charging power. A system can include a programmable radio-frequency generator capable of generating a beam of electromagnetic pulsed radiation and plurality of solid-state amplifiers to amplify the beam of electromagnetic pulsed radiation. The amplified beam of electromagnetic pulsed radiation can be configured to wirelessly charge electronic devices at distances greater than about 100 meters.Type: GrantFiled: September 20, 2023Date of Patent: March 4, 2025Assignee: Epirus Inc.Inventors: Harry Bourne Marr, Jr., William Griffin Dower, Yiu Man So, Jar Jueh Lee, Jeffery Jay Logan
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Patent number: 12237948Abstract: Communication links, computing systems, and methods for their use. The communication link includes a low-voltage differential signaling (LVDS) driver. The LVDS driver is configured to provide a differential signal that is based on a digital bit stream. The digital bit stream includes a series of digital bits that are temporally arranged based on a nominal bit period. The communication link also includes a controllable delay device. The controllable delay device is configured to provide a delay signal to the LVDS driver so as to cause a rising edge or a falling edge of respective digital bits to vary in time with respect to the nominal bit period based on a predetermined sequence of delay amounts. The delay amounts represent positive and negative differences in time from the nominal bit period.Type: GrantFiled: December 19, 2022Date of Patent: February 25, 2025Assignee: Waymo LLCInventors: Kaushik Kannan, Pieter Kapsenberg, Pierre-Yves Droz
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Patent number: 12231104Abstract: A variable attenuator circuit is disclosed. The variable attenuator circuit comprises a plurality of varactor diodes configured to attenuate an RF signal between an RF input and an RF output; a reference voltage input, and a control voltage input configured to vary the attenuation of the variable attenuator circuit based upon a control voltage. A radio frequency module and wireless device comprising said variable attenuator are also provided.Type: GrantFiled: March 8, 2023Date of Patent: February 18, 2025Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Gordon Glen Rabjohn, Anatoli Pukhovski, Pietro Natale Alessandro Chyurlia
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Patent number: 12231117Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.Type: GrantFiled: July 3, 2023Date of Patent: February 18, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITEDInventors: Lei Pan, Yaqi Ma, Jing Ding, Zhang-Ying Yan