Patents Examined by Jung Kim
  • Patent number: 11662757
    Abstract: A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 30, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Marko Koski, Edgar Marti-Arbona, Gordon Lee, Anish Muttreja, Ravi Jenkal
  • Patent number: 11658628
    Abstract: A semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventor: Takaya Yamamoto
  • Patent number: 11658625
    Abstract: A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto Modaffari
  • Patent number: 11652478
    Abstract: A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 16, 2023
    Assignee: WOLFSPEED, INC.
    Inventors: Austin Curbow, Daniel Martin
  • Patent number: 11652479
    Abstract: A method of controlling a half-bridge circuit includes receiving an analog feedback signal proportional to an output of the half-bridge circuit, comparing the received analog feedback signal with a threshold value, selecting a digital feedback signal based on a result of the comparing, comparing the digital feedback signal with a digital reference signal to generate a digital error signal, integrating the digital error signal to generate an integration error signal, downscaling the integral error signal to generate a downscaled integration signal, sampling the downscaled integration signal to generate a sampled integration signal, and generating pulsed signals from the sampled integration signal to provide an input to the half-bridge circuit.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: May 16, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Maiocchi, Ezio Galbiati, Michele Boscolo Berto, Maurizio Ricci
  • Patent number: 11652473
    Abstract: The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 16, 2023
    Assignee: WOLFSPEED, INC.
    Inventors: Austin Curbow, Daniel Martin
  • Patent number: 11647313
    Abstract: An image sensor may include an array of image sensor pixels. The array of image sensor pixels may be controlled by row driver circuitry. The row driver circuitry may include row drivers that receive power supply signals from transconductance amplifier circuitry. The transconductance amplifier circuitry may include multiple amplifiers with output ports shorted to one another. Each amplifier may include input transistors, cross-coupled transistors with a low threshold voltage, and additional transistors coupled in series with the cross-coupled transistors and having a moderate or high threshold voltage.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 9, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Anilkumar Prathipati
  • Patent number: 11641192
    Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: May 2, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
  • Patent number: 11641200
    Abstract: A method for the delivery of power to subthreshold (sub-Vt) circuits uses unused current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Algorithmic and circuit techniques use dynamic management of idle cores when reusing the leakage current of the idle cores. A scheduling algorithm, longest idle time-leakage reuse (LIT-LR) enables energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the switch and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a usage ranking based algorithm, longest idle time-simultaneous leakage reuse and power gating (LIT-LRPG) enables simultaneous implementation of power gating (PG) and leakage reuse in a multiprocessor system-on-chip (MPSoC) platform.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 2, 2023
    Assignee: Drexel University
    Inventors: Md Shazzad Hossain, Ioannis Savidis
  • Patent number: 11640524
    Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 2, 2023
    Assignee: The Government of the United States as represented by the Director, National Security Agency
    Inventor: David J Mountain
  • Patent number: 11637551
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 11636987
    Abstract: The invention relates to a switch including a switch housing, a contact system and a base disposed in the switch housing, a resistive element for diagnosing a state of a switch, and at least two terminals leading from the base. The resistive element has a specific resistance value. The resistive element is a conductive material formed on the base, the terminals being electrically connected by the conductive material.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 25, 2023
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Joerg Gassmann, Felix Weidlich, Jens Penning, Michael Doecker, Jörn Brennenstuhl, Alexander Kunz, Andrea Straniero
  • Patent number: 11637553
    Abstract: An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 25, 2023
    Assignee: QUALCOMM INCORPOATED
    Inventors: Patrick Isakanian, Satish Krishnamoorthy
  • Patent number: 11630134
    Abstract: A rapid sensing value estimation circuit and a method thereof are provided. The circuit includes a first sensing unit, an integration sensing circuit and a rapid estimation circuit. The rapid estimation circuit includes a clock generator, a second counter, a first digital comparator, an arithmetic module and a remainder calculation module. The clock generator generates a clock signal with a first frequency. The second counter counts the clock signal within the integration time to generate a second count value. The first digital comparator determines whether the second count value exceeds a first predetermined count value when the first count value increases. The arithmetic module calculates an estimated count value result and a remainder, and the remainder calculation module can further calculate and estimate values of decimal places of this signal based on the remainder.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 18, 2023
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Jia-Hua Hong
  • Patent number: 11627885
    Abstract: There is provided a technique configured to measure blood pressure with high accuracy. A pulse wave is acquired from each of a plurality of regions on a body surface of a subject, at least two regions are selected from among the plurality of regions in accordance with signal quality of the acquired pulse wave of each region, and blood pressure information is calculated with reference to pulse wave propagation information indicating pulse wave propagation between the at least two regions selected.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 18, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Rieko Ogawa, Yoshihisa Adachi, Yuki Edo, Ryota Tomizawa
  • Patent number: 11632091
    Abstract: A differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: April 18, 2023
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Philippe Pignolo, Pawel Fiedorow, Vincent Rabary
  • Patent number: 11630665
    Abstract: A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 18, 2023
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventor: Lionel Cimaz
  • Patent number: 11626826
    Abstract: A driver may comprise a first node, a second node, and processing circuitry. The first node is configured to receive a command from controller circuitry. The second node is configured to receive a commutation signal for activating or deactivating a switch. The processing circuitry is configured to determine, based on the received command, an activation setting for an activation characteristic for the switch and a deactivation setting for a deactivation characteristic for the switch and drive the switch based on the commutation signal. To drive the switch, the processing circuitry is configured to change, at a first time, the deactivation characteristic for the switch from a previous deactivation setting to the determined deactivation setting and change, at a second time that is different from the first time, the activation characteristic for the switch from a previous activation setting to the determined activation setting.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Michael Krug
  • Patent number: 11623105
    Abstract: Methods, apparatus, and systems for medical procedures are disclosed herein and include applying an ablation electrode of a catheter to a surface of a tissue area, providing a first energy to the ablation electrode applied on the surface of the tissue area to ablate the tissue area, inserting a catheter needle of the catheter to a first distance into the tissue area, through the surface of the tissue area, depositing, via the catheter needle, a first radioactive seed at the first distance, and damaging a second portion of the tissue area based on depositing the first radioactive seed at the first distance.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 11, 2023
    Assignee: Biosense Webster (Israel) Ltd.
    Inventors: Israel Zilberman, Assaf Govari, Gili Attias
  • Patent number: 11617530
    Abstract: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 4, 2023
    Assignee: BioSig Technologies, Inc.
    Inventors: Budimir S. Drakulic, Sina Fakhar, Thomas G. Foxall, Branislav Vlajinic