Abstract: A calibration control circuit includes an off-chip calibration circuit, an on-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a user. The on-chip calibration circuit is configured to receive an enable signal and perform a ZQ self-calibration process on the memory to obtain a second calibration code adapted to a current environmental parameter when the enable signal is in an active state. The mode switching circuit is configured to receive a calibration mode signal, the first calibration code and the second calibration code, and determine the first calibration code as a ZQ calibration code when the calibration mode signal indicates an off-chip calibration mode, or, determine the second calibration code as the ZQ calibration code when the calibration mode signal indicates an on-chip calibration mode.

Abstract: Techniques for designing, creating, and utilizing a current biased tunable qubit are presented. A qubit device can comprise a first Josephson junction (JJ) located along a first current path of the device, and a second JJ and third JJ coupled in series along a second current path in parallel with the first current path, wherein the second and third JJs facilitate controlling frequency of the device. The first JJ can be larger in area than each of the second and third JJs, wherein a current splitting ratio between the first current path and second current path can be increased thereby. The device can comprise a capacitor with a first terminal associated with the second and third JJs, and a second terminal associated with ground. Alternatively, a high kinetic inductance wire can be used in the first current path, instead of the JJ.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.

Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.

Abstract: A power supply control semiconductor device that generates and outputs a drive pulse to turn on and off a switch, which is configured to intermittently supply a current to a primary winding of a voltage conversion transformer, in response to input of a voltage proportional to the current flowing through the primary winding of the voltage conversion transformer and an output voltage detection signal from a secondary side of the voltage conversion transformer is provided. The power supply control semiconductor device is in a no-lead resin-sealed package. The package includes external terminals including a first terminal as an input terminal, a second terminal provided next to the first terminal, and third terminals that have a lower breakdown voltage relative to the first terminal and are different from the second terminal. An interval between the first terminal and the second terminal is wider than each interval between the third terminals.

Abstract: A semiconductor device includes an input terminal, an output terminal, and a plurality of transistors. The transistors are coupled through serial coupling. The transistors include a first transistor and a second transistor. The first transistor has a first end and a second end. The second transistor has a third end, a fourth end, a first gate, and a first body. The third end is coupled to the second end. The semiconductor device further includes a third transistor and a first diode. The third transistor and the first diode are serially coupled between the first body and the first end. The third transistor includes a second gate coupled to the first gate.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.

Abstract: A voltage generation circuit includes a voltage dividing circuit configured to divide applied voltage; a bias circuit configured to generate voltage by dividing power source voltage supplied through a first input terminal; and a power source switching control circuit configured to perform first processing of preventing voltage supply from a power source line to the voltage dividing circuit, connecting the power source line to a first output terminal, and connecting a ground to a second output terminal, second processing of connecting the power source line and the ground to the voltage dividing circuit, and third processing of obtaining voltage through the voltage dividing circuit by supplying voltage generated by the bias circuit to the first output terminal and supplying the voltage generated by the bias circuit to the voltage dividing circuit.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A high-frequency power supply device, which outputs high-frequency pulses to a target device on the basis of a synchronous pulse and a clock pulse, and the output control method therefor are such that a period reference signal is generated from output timing information pertaining to the synchronous pulse, an output level signal is generated from output level information, an output stop time is timed on the basis of the period reference signal and an output stop signal is generated, and, when the period reference signal, the output level signal, and the clock pulse are received and a high-frequency pulse is formed on the basis of these signals, transmission of the output level signal is stopped while the output stop signal is being received.

Abstract: A power conversion system includes: a first power converter to perform power conversion between a first AC system and a DC circuit; and a second power converter to perform power conversion between a second AC system and the DC circuit. Each of the first power converter and the second power converter includes a plurality of submodules connected in series. Each of the plurality of submodules includes a plurality of switching elements and a capacitor. A first fundamental frequency of the first AC system is greater than a second fundamental frequency of the second AC system. A first average voltage value of a capacitor in a first submodule included in the first power converter is larger than a second average voltage value of a capacitor in a second submodule included in the second power converter.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: A switch circuit electrically connected to a power source and a first control source and including a plurality of switch bridge arms is provided. Each of the plurality of switch bridge arms includes a first switch and a second switch electrically connected in series. A loop formed by the first switch, the second switch and the power source is defined as a power loop. A loop formed by the first control source and the first switch is defined as a first control loop. A first mutual inductance is formed between the power loop and the first control loop. Among all the first switches, the first switch with the longer power loop has the smaller first mutual inductance.

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

Abstract: In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.

Abstract: Work vehicle systems include multilayer wiring panels (MWPs), which provide electrical interconnections to various electronic devices integrated into the work vehicle system. A work vehicle system includes a work vehicle component having a component housing which a first MWP is mounted. The first MWP includes a multilayer panel body having a non-planar cross-sectional shape generally conformal with a topology of a non-planar mounting surface of the component housing, preplaced wires embedded in the multilayer panel body, and panel input/output (I/O) interfaces electrically connected by the preplaced wires. The panel I/O interfaces contain first and second panel I/O interfaces electrically coupled to the controller and to the first integrated electronic device, respectively, such that the controller is placed in signal communication with the first integrated electronic device through the first MWP during operation of the work vehicle system.

Abstract: A sense amplifier circuit includes: a charge module configured to charge a set signal node and a reset signal node according to a clock signal; and a sense module configured to sense and amplify a differential input signal according to the clock signal; where, the sense module includes a first amplification circuit, a second amplification circuit, and a cross hopping transfer circuit cross-connected between the first amplification circuit and the second amplification circuit. The cross hopping transfer circuit is configured to transfer a valid signal of a newly started amplification circuit to another amplification circuit if sensing is completed and the differential input signal hops, such that a set signal/reset signal remains unchanged. A flip-flop includes the sense amplifier circuit.

Abstract: A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.

Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.