Patents Examined by Jung Kim
  • Patent number: 12009759
    Abstract: A power conversion system includes: a first power converter to perform power conversion between a first AC system and a DC circuit; and a second power converter to perform power conversion between a second AC system and the DC circuit. Each of the first power converter and the second power converter includes a plurality of submodules connected in series. Each of the plurality of submodules includes a plurality of switching elements and a capacitor. A first fundamental frequency of the first AC system is greater than a second fundamental frequency of the second AC system. A first average voltage value of a capacitor in a first submodule included in the first power converter is larger than a second average voltage value of a capacitor in a second submodule included in the second power converter.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 11, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshiyuki Kono, Shuhei Fujiwara, Ryosuke Uda, Takuya Kajiyama, Toshiyuki Fujii
  • Patent number: 12003239
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chia Lai, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
  • Patent number: 12003232
    Abstract: A switch circuit electrically connected to a power source and a first control source and including a plurality of switch bridge arms is provided. Each of the plurality of switch bridge arms includes a first switch and a second switch electrically connected in series. A loop formed by the first switch, the second switch and the power source is defined as a power loop. A loop formed by the first control source and the first switch is defined as a first control loop. A first mutual inductance is formed between the power loop and the first control loop. Among all the first switches, the first switch with the longer power loop has the smaller first mutual inductance.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: June 4, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Boyi Zhang, Ruxi Wang, Peter Mantovanelli Barbosa
  • Patent number: 12003243
    Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: June 4, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumit Dubey, Jasjot Singh Chadha
  • Patent number: 11987187
    Abstract: Work vehicle systems include multilayer wiring panels (MWPs), which provide electrical interconnections to various electronic devices integrated into the work vehicle system. A work vehicle system includes a work vehicle component having a component housing which a first MWP is mounted. The first MWP includes a multilayer panel body having a non-planar cross-sectional shape generally conformal with a topology of a non-planar mounting surface of the component housing, preplaced wires embedded in the multilayer panel body, and panel input/output (I/O) interfaces electrically connected by the preplaced wires. The panel I/O interfaces contain first and second panel I/O interfaces electrically coupled to the controller and to the first integrated electronic device, respectively, such that the controller is placed in signal communication with the first integrated electronic device through the first MWP during operation of the work vehicle system.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: May 21, 2024
    Assignee: DEERE & COMPANY
    Inventors: Kunal Gupta, Nakib Y. Siddiqui, Bala Naga Mani Lakshmi Bhavani Gudimetla
  • Patent number: 11990900
    Abstract: In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 21, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Huangpeng Zhang, Shiyang Yang
  • Patent number: 11979121
    Abstract: A sense amplifier circuit includes: a charge module configured to charge a set signal node and a reset signal node according to a clock signal; and a sense module configured to sense and amplify a differential input signal according to the clock signal; where, the sense module includes a first amplification circuit, a second amplification circuit, and a cross hopping transfer circuit cross-connected between the first amplification circuit and the second amplification circuit. The cross hopping transfer circuit is configured to transfer a valid signal of a newly started amplification circuit to another amplification circuit if sensing is completed and the differential input signal hops, such that a set signal/reset signal remains unchanged. A flip-flop includes the sense amplifier circuit.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Dandan Shi, Qifan Gong
  • Patent number: 11978498
    Abstract: A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yu Li, Teng Shi
  • Patent number: 11979156
    Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: May 7, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
  • Patent number: 11973495
    Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 30, 2024
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Patent number: 11967355
    Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 11967956
    Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 23, 2024
    Assignee: Quantum Machines
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
  • Patent number: 11967629
    Abstract: A semiconductor device and methods of fabricating and using the same are provided. The semiconductor device comprises a channel region and at least a first, second, and third electrode. The channel region includes a compound having a transition metal and a chalcogen. The thickness of the channel region is about 3 to about 40 atomic layers.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: April 23, 2024
    Assignees: Kansas State University Research Foundation, Purdue Research Foundation
    Inventors: Suprem R. Das, David B. Janes, Jiseok Kwon
  • Patent number: 11967957
    Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 23, 2024
    Assignee: Quantum Machines
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
  • Patent number: 11962146
    Abstract: A system for controlling a bipolar DC power includes a positive conductor, a neutral conductor and negative conductor. A positive pole-to-neutral voltage is a voltage between the positive conductor and the neutral conductor and a negative pole-to-neutral voltage is a voltage between the negative conductor and the neutral conductor. The system comprises control means for controlling the positive pole-to-neutral voltage and the negative pole-to-neutral voltage. The control means includes a first voltage converter configured to control a sum or difference of the positive pole-to-neutral voltage and the negative pole-to-neutral voltage, respectively as a function of the sum or difference of the positive output current and negative output current, and a second voltage converter.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 16, 2024
    Assignee: KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Johan Driesen, Giel Van Den Broeck
  • Patent number: 11955960
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: April 9, 2024
    Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
    Inventors: Ke-Horng Chen, Tzu-Hsien Yang, Yong-Hwa Wen, Kuo-Lin Cheng
  • Patent number: 11949408
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature sensor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: April 2, 2024
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11945399
    Abstract: A vehicle ignition interlock device comprises a vehicle ignition locking circuit which relies upon Bluetooth® pairing with a matching cellular phone to enable the ignition. The device is housed in a plastic enclosure having inside a Bluetooth® connection module and a relay that are interconnected to wiring. External wiring then connects the device to vehicle power, ignition interlock, and a valet switch. A valet switch allows the device to be overridden. During initial installation or setup, the device is paired with authorized cellular phones. During use, the owner approaches the vehicle whereupon the device automatically pairs with the phone and enables the ignition. Should the phone not be present, the vehicle will not start.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 2, 2024
    Inventor: Larry V. Ruthven
  • Patent number: 11940302
    Abstract: A displacement measurement device for a sensing device. The sensing device includes a first displacement sensor. The displacement measurement device includes: a drive signal generating circuit configured to output a drive signal to the first displacement sensor; a first signal processing circuit configured to receive a signal from the first displacement sensor and output a first ADSO signal; and a computing device including a first timer. The first timer is configured to receive a CLK512 signal and the first ADSO signal, and time or count according to the CLK512 signal and the first ADSO signal; and the CLK512 signal is a square wave signal related to a period and phase of the drive signal.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: March 26, 2024
    Assignee: GUILIN GEMRED SENSOR TECHNOLOGY ASSIGNEE CO., LTD.
    Inventors: Guangjin Li, Jian Shi, Bingheng Li
  • Patent number: 11936347
    Abstract: An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock generator, a plurality of analog-to-digital converters, low and high-speed communications interfaces, drain and gate sensing circuits (that can include one or more current sense amplifiers), and a gate driver circuit. The ASIC can be a low voltage semiconductor integrated circuit.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 19, 2024
    Assignee: Epirus, Inc.
    Inventors: Padraig James Cooney, Denpol Kultran, Ronald Chang, Harry Bourne Marr, Jr.