Patents Examined by Jung Kim
  • Patent number: 11751491
    Abstract: Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 5, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isaac Lauer, Neereja Sundaresan
  • Patent number: 11742841
    Abstract: A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vibha Goenka
  • Patent number: 11742811
    Abstract: An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas K. Pulijala
  • Patent number: 11742654
    Abstract: A disclosed under-voltage lockout (UVLO) circuit includes an automatic UVLO threshold configuration. The UVLO circuit may include an over-voltage protection circuit that receives power from a power source, a peak detector that detects a peak voltage output for the power source, a voltage threshold generator that sets a UVLO threshold based on the peak voltage output, and a comparator that compares an instantaneous voltage with the UVLO threshold and configures an operating mode of a device based on the comparison.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: August 29, 2023
    Assignee: CalAmp Corp.
    Inventors: Justin Flor, Russell Cook
  • Patent number: 11728778
    Abstract: A transceiver that may be implemented in low-voltage differential signaling (LVDS) transmission system or a multipoint LVDS transmission system, and corresponding systems are disclosed herein. The transceiver can filter a common-mode component of a differential input signal input into the transceiver while maintaining a high impedance for a differential-mode component of the differential input signal. The transceiver utilizes teeter-totter circuitry to maintain the high impedance for the differential-mode component of the differential input signal.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 15, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Andreas Koch, Ralph McCormick, Brian B. Moane
  • Patent number: 11714640
    Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11716079
    Abstract: A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 1, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michal Olsak, Pavel Baros
  • Patent number: 11709186
    Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: July 25, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
  • Patent number: 11711078
    Abstract: An ON/OFF detection device is configured to detect ON/OFF of an input unit using a load sensor, and includes a threshold setting unit, a comparison unit, and an ON/OFF determination unit. The threshold setting unit is configured to set a threshold value with respect to a previous detection value of the load sensor. The comparison unit is configured to compare the threshold value and a current detection value. The ON/OFF determination unit is configured to determine ON/OFF of the input unit based on a comparison result. When a previous determination result of the ON/OFF determination unit is ON, the threshold setting unit is configured to set the threshold value to be lower than the previous detection value. When the previous determination result of the ON/OFF determination unit is OFF, the threshold setting unit is configured to set the threshold value to be higher than the previous detection value.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 25, 2023
    Assignee: Marells Corporation
    Inventor: Hideto Ujiie
  • Patent number: 11710060
    Abstract: A method, apparatus, system, and computer program product for quantum processing. A target quantum programming for a process for a quantum computer is identified. A universal gate set is selected based on a computer type. Any operation possible for a particular quantum computer can be performed using the universal gate set. Instructions for the process in a source quantum programming language are sent to a source quantum language translator which outputs a digital model representation of quantum computer components that are arranged to perform the process using the instructions. The digital model representation of the quantum computer components and the universal gate set are sent to a target quantum language translator, which outputs the instructions for operations for the process in a target quantum programming language using the digital model representation of the quantum computer components and the universal gate set for the computer type for the quantum computer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 25, 2023
    Assignee: The Boeing Company
    Inventors: Richard Joel Thompson, Marna M. Kagele
  • Patent number: 11709673
    Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11703901
    Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: July 18, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Jean Camiolo, Alexandre Pons
  • Patent number: 11699995
    Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: July 11, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Vaibhav Garg, Abhishek Jain, Anand Kumar
  • Patent number: 11695007
    Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiang Wang, Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 11695413
    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: July 4, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: Lei Pan, Yaqi Ma, Jing Ding, Zhang-Ying Yan
  • Patent number: 11695483
    Abstract: Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isaac Lauer, Neereja Sundaresan
  • Patent number: 11689198
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: June 27, 2023
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11681318
    Abstract: A voltage generation circuit includes a voltage dividing circuit configured to divide an applied voltage; a bias circuit configured to generate a voltage by dividing a power source voltage supplied through a first input terminal; and a power source switching control circuit. The power source switching control circuit is configured to perform first processing of preventing a voltage supply from a power source line to the voltage dividing circuit, connecting the power source line to a first output terminal, and connecting a ground to a second output terminal, second processing of connecting the power source line and the ground to the voltage dividing circuit, and third processing of obtaining a voltage through the voltage dividing circuit by supplying a voltage generated by the bias circuit to the first output terminal and supplying the voltage generated by the bias circuit to the voltage dividing circuit.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: June 20, 2023
    Assignee: Kioxia Corporation
    Inventor: Koji Ooiwa
  • Patent number: 11677392
    Abstract: Passive gate bias network topologies are implemented for stacked FET switch structures, which improve the settling time and low cut-off frequency for both DC and non-DC operation. DC capable stacked switch bias structures provide gate and bulk bias voltages, using input DC voltages, which are coupled to the gate terminals and the bulk terminals of the stacked switches. The DC coupling can be achieved using resistors, or a combination of resistors and diodes. An exemplary SPST switch includes a series stacked switch in combination with a shunt stacked switch, which can be controlled between alternating states. For low cut-off frequency improvement structures, an input signal is coupled to the gate terminals and bulk terminals of the switches in the stacked switches, using a DC block capacitor and resistors. The low cut-off of the bulk can be improved by connecting the bulk terminal of one switch to the opposite polarity switch.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: June 13, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Ercan Kaymaksut, Mehmet Arda Akkaya, Murat Davulcu, Turusan Kolcuoglu
  • Patent number: 11671098
    Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: June 6, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kyoung Min Lee, James M. Walden, Brian Linehan, Yang Zhang