Patents Examined by Jung Kim
  • Patent number: 11967957
    Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 23, 2024
    Assignee: Quantum Machines
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
  • Patent number: 11967629
    Abstract: A semiconductor device and methods of fabricating and using the same are provided. The semiconductor device comprises a channel region and at least a first, second, and third electrode. The channel region includes a compound having a transition metal and a chalcogen. The thickness of the channel region is about 3 to about 40 atomic layers.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: April 23, 2024
    Assignees: Kansas State University Research Foundation, Purdue Research Foundation
    Inventors: Suprem R. Das, David B. Janes, Jiseok Kwon
  • Patent number: 11967355
    Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 11962146
    Abstract: A system for controlling a bipolar DC power includes a positive conductor, a neutral conductor and negative conductor. A positive pole-to-neutral voltage is a voltage between the positive conductor and the neutral conductor and a negative pole-to-neutral voltage is a voltage between the negative conductor and the neutral conductor. The system comprises control means for controlling the positive pole-to-neutral voltage and the negative pole-to-neutral voltage. The control means includes a first voltage converter configured to control a sum or difference of the positive pole-to-neutral voltage and the negative pole-to-neutral voltage, respectively as a function of the sum or difference of the positive output current and negative output current, and a second voltage converter.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 16, 2024
    Assignee: KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Johan Driesen, Giel Van Den Broeck
  • Patent number: 11955960
    Abstract: The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: April 9, 2024
    Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
    Inventors: Ke-Horng Chen, Tzu-Hsien Yang, Yong-Hwa Wen, Kuo-Lin Cheng
  • Patent number: 11945399
    Abstract: A vehicle ignition interlock device comprises a vehicle ignition locking circuit which relies upon Bluetooth® pairing with a matching cellular phone to enable the ignition. The device is housed in a plastic enclosure having inside a Bluetooth® connection module and a relay that are interconnected to wiring. External wiring then connects the device to vehicle power, ignition interlock, and a valet switch. A valet switch allows the device to be overridden. During initial installation or setup, the device is paired with authorized cellular phones. During use, the owner approaches the vehicle whereupon the device automatically pairs with the phone and enables the ignition. Should the phone not be present, the vehicle will not start.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 2, 2024
    Inventor: Larry V. Ruthven
  • Patent number: 11949408
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature sensor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: April 2, 2024
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11940302
    Abstract: A displacement measurement device for a sensing device. The sensing device includes a first displacement sensor. The displacement measurement device includes: a drive signal generating circuit configured to output a drive signal to the first displacement sensor; a first signal processing circuit configured to receive a signal from the first displacement sensor and output a first ADSO signal; and a computing device including a first timer. The first timer is configured to receive a CLK512 signal and the first ADSO signal, and time or count according to the CLK512 signal and the first ADSO signal; and the CLK512 signal is a square wave signal related to a period and phase of the drive signal.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: March 26, 2024
    Assignee: GUILIN GEMRED SENSOR TECHNOLOGY ASSIGNEE CO., LTD.
    Inventors: Guangjin Li, Jian Shi, Bingheng Li
  • Patent number: 11936375
    Abstract: A buffer apparatus, a chip and an electronic device. The apparatus comprises: a voltage adjustment module (10) comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module (10) is used for receiving an input voltage, using a threshold voltage for the first PMOS to adjust the input voltage, and outputting a driving voltage; and a buffer module (20) electrically connected to the voltage adjustment module (10) and used for receiving an input signal, buffering the input signal under the driving voltage, and outputting a buffered signal. The driving voltage obtained by using the threshold voltage for the first PMOS to adjust the input voltage can compensate for a process corner of the buffer module (20), such that the range of a flip point voltage of the buffer module (20) becomes small and meets process requirements.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 19, 2024
    Assignee: Chipone Technology (Beijing) Co., LTD.
    Inventors: Wei Yang, Lei Fan
  • Patent number: 11936347
    Abstract: An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock generator, a plurality of analog-to-digital converters, low and high-speed communications interfaces, drain and gate sensing circuits (that can include one or more current sense amplifiers), and a gate driver circuit. The ASIC can be a low voltage semiconductor integrated circuit.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 19, 2024
    Assignee: Epirus, Inc.
    Inventors: Padraig James Cooney, Denpol Kultran, Ronald Chang, Harry Bourne Marr, Jr.
  • Patent number: 11923831
    Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 5, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 11922299
    Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: March 5, 2024
    Assignee: The Government of the United States as represented by the Director, National Security Agency
    Inventor: David J. Mountain
  • Patent number: 11923839
    Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Dirk Priefert, Matteo Albertini, Remigiusz Viktor Boguszewicz
  • Patent number: 11923816
    Abstract: An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 5, 2024
    Assignee: CAMBRIDGE GAN DEVICES LIMITED
    Inventors: Martin Arnold, Loizos Efthymiou, Florin Udrea, John William Findlay, Giorgia Longobardi
  • Patent number: 11923838
    Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: March 5, 2024
    Assignee: PSEMI CORPORATION
    Inventors: Alper Genc, Peter Bacon
  • Patent number: 11914411
    Abstract: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Shylaja Krishnan, Tallam Vishwanath, Akshay Yashwant Jadhav
  • Patent number: 11916543
    Abstract: An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT<VSH?(2×VGT), in a case where the enable signal is 0, the second gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of a PMOS when the control signal is 0, and the first gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of an NMOS when the control signal is 1.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shigeo Imai
  • Patent number: 11909400
    Abstract: A method and apparatus for generating an RF signal uses digital signal components to generate a synthesized RF signal having a plurality of frequency components. An analog filter is used to filter the synthesized RF signal. The analog filter is a tunable, active feedback circuit having one or more variable resonators and a variable gain block connected in a signal loop that is defined by a passband. The analog filter is tuned such that the passband of the analog filter overlaps one or more desired frequency components of the plurality of frequency components of the synthesized RF signal, and such that the passband has a relative bandwidth of about 1% or less.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 20, 2024
    Assignee: Anlotek Limited
    Inventor: Jorgen Staal Nielsen
  • Patent number: 11909398
    Abstract: Laboratory equipment with flammable refrigerant and connected to at least two different electrical potentials for supplying the equipment with electrical energy. An electrical switch arrangement has first and second switches for electrical separation from, respectively, the first and second potentials. A sequence controller switches on the first switch and thereafter the second switch. A monitoring device is connected via a first contact on the equipment side to the first switch and via a second contact on the mains side to an electrical potential other than the first electrical potential for detecting a switched-on state of the first switch and signaling the detection to the sequence controller. When the monitoring device signals a switched-on state, the sequence controller blocks operation of the equipment as a function of the signaled switched-on state and whether the first switch is expected to be switched on or switched off.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Eppendorf SE
    Inventors: Uwe Beukert, Falk Binder
  • Patent number: 11901888
    Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Vedant Sadashiv Chendake, Giuseppe Bernacchia, Pablo Yelamos Ruiz