Abstract: One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.

Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive? voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: A device for preventing a signal induced by hazardous EMI on a power line in a group of multiple adjacent, parallel power lines of the same phase in an electrical power system from reaching an electrical component connected to one of the multiple power lines, the device comprising at least one conductive impedance transition element having a disk-shaped structure with multiple holes for receiving the multiple adjacent power lines of the same phase, the disk-shaped structures each having an outer diameter that is greater than diameter of all of the multiple parallel power lines to deliberately create an impedance mismatch between the conductive impedance transition elements and adjacent portions of the multiple power lines. The impedance mismatch causes the conductive impedance transition elements to reflect high-frequency components of a signal induced on the multiple power lines by hazardous EMI and the high-frequency components are reflected and dissipated as heat.

Abstract: An off chip driving system includes a decision circuit, multiple first and second adjustable-enhancement circuits, and multiple first and second drivers. The decision circuit outputs a first and a second decision signal according to a clock and an input data. Each first adjustable-enhancement circuit generates one of first control signals in response to the first and the second decision signal and one of first optional signals. Each second adjustable-enhancement circuit generates one of second control signals in response to the first and the second decision signal and one of second optional signals. Each first driver is coupled to the corresponding first adjustable-enhancement circuit and configured to be enabled in response to the corresponding first control signal. Each second driver is coupled to the corresponding second adjustable-enhancement circuit and configured to be enabled in response to the corresponding second control signal.

Abstract: A readout circuit, an image sensor and an electronic device are provided, which could effectively reduce an area and power consumption of the image sensor. The readout circuit includes a plurality of capacitors, a switch circuit and an output circuit; where the plurality of capacitors are connected to the output circuit through the switch circuit; the plurality of capacitors are configured to store output signals of a plurality of pixel circuits, respectively; and the output circuit is configured to output signals stored by the plurality of capacitors through the switch circuit one-by-one.

Abstract: A switch for a radio frequency signal switch assembly including a first node coupled to one of an input and an output of the switch assembly and a second node coupled to a reference voltage, a control node, a common resistor coupled to the control node, a plurality of transistors coupled between the first and second nodes, each transistor of the plurality of transistors having a gate, a drain, and a source, and a plurality of gate resistors coupled between the common resistor and the gates of the plurality of transistors, the plurality of gate resistors having a scaled arrangement of values selected based on a voltage differential across each of the plurality of gate resistors to improve switching speed.

Abstract: The present invention provides a circuit including a reference voltage generator and a plurality of receivers, wherein the reference voltage generator is configured to generate a reference voltage, and each of the receivers is configured to receive the reference voltage and a corresponding input signal to generate a corresponding output signal. In addition, for at least a specific receiver of the plurality of receivers, the specific receiver comprises at least one amplifying stage, the amplifying stage comprises a first input terminal configured to receive the corresponding input signal, a second input terminal configured to receive the reference voltage, a first output terminal configured to generate a first signal, and a second output terminal configured to generate a second signal; and the specific receiver further comprises a first feedback circuit coupled between the first output terminal and the second input terminal.

Abstract: An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage VBIAS with respect to a CM voltage VCM. The CM voltage VCM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

Abstract: A self-biased differential transmitter is provided. The transmitter may include a differential output driver powered by a supply voltage provided by a differential signal receiver. The output driver may include a bias voltage generator to generate bias voltages to enable one or more transistors in the output driver to operate with differential signals that are beyond the safe operating voltage range of transistors included within the differential transmitter.

Abstract: A high-voltage output driver (1) for a sensor device (100) with reverse current blocking comprises a supply node (SN) to apply a supply voltage (VHV) and an output node (OP) to provide an output signal (OS) of the high-voltage output driver (1). The high-voltage output driver (1) comprises a driver transistor (MP0) being disposed between the supply node (SN) and the output node (OP). The high-voltage output driver (1) further comprises a bulk control circuit (20) to apply a bulk control voltage (Vwell) to a bulk node (BMP0) of the driver transistor (MP0), and a gate control circuit (30) to apply a gate control voltage (GCV) to the gate node (GMP0) of the driver transistor (MP0).

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods is disclosed. An apparatus includes a pull-up SCRC transistor, a pull-down SCRC transistor, and a charge transfer circuit. The pull-up SCRC transistor includes a pull-up gate terminal. The pull-down SCRC transistor includes a pull-down gate terminal. The charge transfer circuit is electrically connected between the pull-up gate terminal and the pull-down gate terminal. The charge transfer circuit is configured to transfer charge between the pull-up gate terminal and the pull-down gate terminal.

Abstract: One example includes a circuit that includes a transistor control circuit having an input and an output adapted to be coupled to the output of the transistor control circuit and can provide a slew-rate compensation voltage proportional to a slew-rate of a control voltage of the transistor. A reference voltage source can be coupled to the slew-rate compensator to provide a reference voltage at the output of the reference voltage source, the slew-rate compensator configured to add the slew-rate compensation voltage to the reference voltage to provide an adjusted reference voltage at the output of the slew rate compensator. A reference comparator having a first input, a second input and an output is coupled to the input of the transistor control circuit. The first input can be coupled to the control terminal of the transistor, and the second input can be coupled to the output of the slew-rate compensator.

Abstract: Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

Abstract: A starting circuit capable of further reducing an influence of a variation in the threshold voltage of a transistor is proposed. The starting circuit includes an N-type first MOS transistor whose threshold voltage is near 0 V, a resistor interposed between a source terminal of the first MOS transistor and a ground, and a control circuit controlling a gate voltage of the first MOS transistor. An amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.

Abstract: The present invention includes self-contained, rechargeable power systems for areas having unreliable electrical grids or no electrical grid at all, and methods related thereto. The system may include one or more solar panels of various sizes to provide an off-grid power generation source, battery receivers for receiving batteries of various chemistries, and a control circuitry that is operable to detect the voltage and/or current output of the batteries that are installed in the system to determine their specific battery chemistry and then adjust the charge algorithm of the batteries to optimize both the charge capacity and the cycle life of the batteries. The control circuitry may also be operable to switch configurations of the solar panels and/or the batteries to optimize performance of the system. The system may be operable to power one or more light emitters and/or external electronic devices connected through the system by a charge port.

Abstract: Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

Abstract: An electrical bonding test device, including a test system circuit configured to generate a current pulse for ground bonding testing of subject units, a first test system connector configured to provide an electrical connection between a first unit connector shell of a first unit of the subject units and the test system circuit and to pass the current pulse to the first unit connector shell during the ground bonding testing, and a second test system connector configured to provide an electrical connection between a second unit connector shell of a second unit of the subject units and a first node of the test system circuit. The test system circuit is further configured to provide an indication indicating whether a bonding path through the subject units is a conductive path having a resistance below a resistance threshold.

Abstract: A radio frequency apparatus and a voltage generating device thereof are provided. The voltage generating device includes a first switch and a second switch. A first terminal of the first switch receives a first voltage. A control terminal of the first switch receives a second voltage. A first terminal of the second switch receives the second voltage. A control terminal of the second switch receives the first voltage. A second terminal of the second switch and a second terminal of the first switch are coupled to an output node, wherein the output node outputs an output voltage related to at least one of the first voltage and the second voltage.