Abstract: A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.

Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

Abstract: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Abstract: A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

Abstract: Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

Abstract: A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

Abstract: The present application relates to electronics and in particular to switch drive circuits and more particularly to galvanically isolated switch circuits with power transfer from the switch driver input side to the switch side. More specifically, the present application provides a switch drive circuit using a single transformer to transfer control signals to a secondary side for control of the switch along with power to a secondary side circuit to drive the switch in response to the control signals. By detecting the control signal first before drawing current, the effects of leakage inductance in the transformer are reduced.

Abstract: A wireless power transmission system includes a first antenna, a second antenna configured to perform wireless power transmission with the first antenna, and a movement unit configured to move a position of the second antenna relative to the first antenna in a predetermined moving direction, wherein the second antenna is shorter in length in the moving direction than the first antenna, wherein a distance between at least one end portion of the first antenna in the moving direction and the second antenna at a position where the second antenna faces the end portion is longer than a distance between an intermediate portion of the first antenna and the second antenna at a position where the second antenna faces the intermediate portion, and wherein the intermediate portion of the first antenna is a portion of the first antenna excluding both end portions of the first antenna.

Abstract: Disclosed is a system and a method to use the system that includes a substrate to support a film of liquid helium and an electron subsystem confined by image forces in a direction perpendicular to the surface of the film, a side gate to electrostatically define a boundary of the electron subsystem, a trap gate to electrostatically define an electron trap located outside the boundary of the electron subsystem, and a load gate to selectively open and close access from the electron subsystem to the electron trap, wherein to open access to the electron trap is to apply a first load gate voltage to the load gate to allow the electrons to access the electron trap, and wherein to close access to the electron trap is to apply a second load gate voltage to the load gate to prevent the electrons from accessing the electron trap.

Abstract: A voltage controlled circuit includes a tracking circuit, an operational amplifier, a transistor, a feedback circuit and a sample and hold circuit. The tracking circuit generates an updated enabling voltage according to an enabling voltage, a sample enabling voltage and a sample reference voltage. The operational amplifier includes a first input terminal used to receive an input voltage, a second input terminal used to receive a feedback voltage, and an output terminal used to output a control voltage. The transistor includes a control terminal used to receive the control voltage, a first terminal used to receive a reference voltage, and a second terminal used to output a regulated voltage. The feedback circuit generates the feedback voltage according to the regulated voltage. The sample and hold circuit is used to sample the input voltage to generate the sample enabling voltage, and sample the feedback voltage to generate the sample reference voltage.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A Quadrature Voltage Controlled Oscillator (Quad VCO) based on standard digital cells and delay cells, is adapted to generate two high-frequency output signals that are “in quadrature”, so they both oscillate with similar frequency while exhibiting a mutual phase offset of about 90 degrees, and a) the digital cells include a mix of digital circuits used for implementing standard flip-flop circuits and standard logic gates; and b) the delay cells include circuits accepting a logic signal at their input and outputting a time-delayed version of said input signal, with a time delay that may be varied by a control voltage analog signal that determines the cell delay.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a buffer amplifier circuit, having an input coupled to Q1 and an output coupled to Q2. The offset of the buffer amplifier circuit can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror, while being able to reduce the buffer offset due to mismatch between master and slave sides of the current mirror circuit.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: A silicon carbide power device is controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.

Abstract: A semiconductor device includes an I/O circuit configured to be supplied with a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage, and to receive an input signal based on the first voltage. The I/O circuit includes an enabler circuit configured to be supplied with the second voltage, and to generate a first signal based on the second voltage, and a first level shifter circuit coupled to the enabler circuit, and configured to, based on the first signal, level-shift a signal based on the second voltage to a signal based on the third voltage.

Abstract: A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.