Abstract: A circuit for charge-balanced current-controlled stimulation. The circuit includes a transistor differential pair, a first current mirror, a second current mirror, and a third current mirror. The transistor differential pair includes a first differential input node, a second differential input node, a first differential output node, a second differential output node, and a common node. The transistor differential pair is configured to generate a first differential current that passes through the first differential output node and a second differential current that passes through the second differential output node. The first current mirror is configured to generate a first mirrored current based on the first differential current. The second current mirror is configured to generate a second mirrored current based on the second differential current. The third current mirror is configured to generate a third mirrored current based on the first mirrored current.

Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

Abstract: A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

Abstract: A power transmitter (101) is arranged to transfer power to a power receiver (105) using a wireless inductive power signal. The power transmitter (101) comprises a power signal generator (207) which drives an inductor (103) to provide the power signal to an inductor of the power receiver (105). A power loop control is employed by the power receiver (105) providing power control error messages to the power transmitter (101). The power transmitter (101) comprises a query message processor (209) which can detect a query message received from the power receiver (105) using load modulation of the power signal. A modification processor (211) is arranged to modify a response of the power loop controller to the power control error messages dependent on the query message. The power receiver (105) can detect the modifications to the operation of the power control and thus can interpret this as a response to the query message.

Abstract: Systems, apparatuses, and methods for implementing low-power flip-flops with balanced clock-to-Q delay are described. A flip-flop includes a primary latch, an upper secondary latch, and a lower secondary latch. The primary latch transmits a data value from an input port to a first node when transparent. The upper secondary latch pulls up a second node when transparent and when the first node is equal to a first value. The second node is a prebuffered data output of the flip-flop. The lower secondary latch pulls down the second node when transparent and when the first node is equal to a second value different from the first value. To ensure the flip-flop has a balanced clock-to-Q delay, a first set of clock signals coupled to transistor gates of the primary latch are delayed with respect to a second set of clock signals coupled to transistor gates of the upper secondary latch.

Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.

Abstract: This document discusses, among other things, a signal receiving circuit, configured to receive an input voltage signal. The signal receiving circuit can comprise an input voltage regulating circuit and a comparing circuit. The input voltage regulating circuit can carry out a waveform pre-regulation for the input voltage signal to obtain a first voltage signal, and the comparing circuit can compare the first voltage signal with a second voltage signal, and output a comparison voltage signal having a pulse width that satisfies a first predetermined condition indicative that the input voltage signal is correctly identifiable. The present document further discusses a signal detecting circuit and a signal receiving method.

Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.

Abstract: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing startups of bandgap reference circuits in memory systems, e.g., non-volatile memory systems.

Abstract: An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2?·fc·C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

Abstract: A charge pump unit structure of a charge pump circuit includes a booster circuit unit, a positive pump transfer unit and a negative pump transfer unit. An output terminal of the booster circuit unit is connected to an input terminal of the positive pump transfer unit through a first switch circuit and to an input terminal of the negative pump transfer unit through a second switch circuit. An erase enable signal is connected to control terminals of the positive and negative pump transfer units. A first enable signal is connected to control terminals of the positive pump transfer unit and the first switch circuit. A second enable signal is connected to control terminals of the negative pump transfer unit and the second switch circuit.

Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

Abstract: A capacitively-driven tunable coupler includes a coupling capacitor connecting an open end of a quantum object (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without breaking the functionality of the object) to an RF SQUID having a Josephson element capable of providing variable inductance and therefore variable coupling to another quantum object.

Abstract: In a gate driver, a comparator input is adapted to be coupled through a resistor and a diode to a first transistor. A latch input is coupled to a comparator output. A second transistor has a first control terminal and a first output terminal. The first output terminal is adapted to be coupled to a control terminal of the first transistor. A third transistor is smaller than the second transistor. The third transistor has a second control terminal and a second output terminal. The second output terminal is adapted to be coupled to the control terminal of the first transistor. Control logic has a logic input and first and second logic outputs. The logic input is coupled to a latch output. The first logic output is coupled to the first control terminal. The second logic output is coupled to the second control terminal.

Abstract: A silicon carbide power device controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.

Abstract: A shippable, balanced, self-contained, solar-powered, battery-charging, restricted-access, parkable, equipment station.

Abstract: A frequency regulator and a frequency regulating method thereof, and an electronic device are disclosed. The frequency regulator includes: a signal processing circuit configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency; and a frequency regulating circuit configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word. The frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during a period that the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.