Abstract: Methods, apparatus, and systems for medical procedures are disclosed herein and include applying an ablation electrode of a catheter to a surface of a tissue area, providing a first energy to the ablation electrode applied on the surface of the tissue area to ablate the tissue area, inserting a catheter needle of the catheter to a first distance into the tissue area, through the surface of the tissue area, depositing, via the catheter needle, a first radioactive seed at the first distance, and damaging a second portion of the tissue area based on depositing the first radioactive seed at the first distance.

Abstract: A driver may comprise a first node, a second node, and processing circuitry. The first node is configured to receive a command from controller circuitry. The second node is configured to receive a commutation signal for activating or deactivating a switch. The processing circuitry is configured to determine, based on the received command, an activation setting for an activation characteristic for the switch and a deactivation setting for a deactivation characteristic for the switch and drive the switch based on the commutation signal. To drive the switch, the processing circuitry is configured to change, at a first time, the deactivation characteristic for the switch from a previous deactivation setting to the determined deactivation setting and change, at a second time that is different from the first time, the activation characteristic for the switch from a previous activation setting to the determined activation setting.

Abstract: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Abstract: Solar array fault detection, classification, and localization using deep neural nets is provided. A fault-identifying neural network uses a cyber-physical system (CPS) approach to fault detection in photovoltaic (PV) arrays. Customized neural network algorithms are deployed in feedforward neural networks for fault detection and identification from monitoring devices that sense data and actuate each individual module in a PV array. This approach improves efficiency by detecting and classifying a wide variety of faults and commonly occurring conditions (e.g., eight faults/conditions concurrently) that affect power output in utility scale PV arrays.

Abstract: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

Abstract: A system and method measures impedance across a plurality of electrodes and assesses proximity or contact between electrodes of a medical device and patient tissue. Contact is assessed between individual electrodes and cardiac tissue using bipolar electrode complex impedance measurements. Initially, baseline impedance values are established for each of the individual electrodes based on the responses of the electrodes to the applied drive signals. After establishing the baseline impedance values a series of subsequent impedance values are measured for each electrode. For each electrode, each subsequent impedance value may be compared to a previous baseline impedance value for that electrode. If a subsequent impedance value is less than the baseline impedance value for a given electrode, the baseline impedance value may be reset to the subsequent impedance value. Such systems and method are particularly applicable to medical devices having numerous electrodes.

Abstract: A system and method measures impedance across a plurality of electrodes and assesses proximity or contact between electrodes of a medical device and patient tissue. Contact is assessed between individual electrodes and cardiac tissue using bipolar electrode complex impedance measurements. Initially, baseline impedance values are established for each of the individual electrodes based on the responses of the electrodes to the applied drive signals. After establishing the baseline impedance values a series of subsequent impedance values are measured for each electrode. For each electrode, each subsequent impedance value may be compared to a previous baseline impedance value for that electrode. If a subsequent impedance value is less than the baseline impedance value for a given electrode, the baseline impedance value may be reset to the subsequent impedance value. Such systems and method are particularly applicable to medical devices having numerous electrodes.

Abstract: A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

Abstract: A power supply device may include a connector configured to electrically couple the power supply device to a conductor of the underground power lines; a voltage divider configured to receive an input voltage from the conductor, the voltage divider comprising a capacitor and divider voltage control electronics in series with the capacitor; and, a surge resistor in series with the capacitor and configured to provide impulse protection from surge events. The divider voltage control electronics may be configured to regulate an output voltage of the voltage divider to support variable loads on the voltage divider.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: Methods and systems for conditioning a signal indicative of electrosurgical unit activity are described. A hardware circuit acquires AC current from an electrosurgical unit on patient isolated circuitry and conditions the signal in either of two alternate processing methods. The processed signal is routed as input to an analog to digital converter circuit. A method for determining saturation on referential inputs and recovering inputs to an unsaturated state is also described.

Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

Abstract: Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Abstract: There is provided an apparatus and method, the apparatus comprising a power input and a switch isolation circuit to provide isolation between the power input and a protected switch responsive to a timing signal. The switch isolation circuit comprises a switch isolation charge store, and a buffer circuit to receive power from the switch isolation charge store and coupled between the timing signal and the protected switch. The switch isolation circuit is configured to, in response to the timing signal having the first value, operate in a powered mode in which the switch isolation charge store receives power from the power input; and, in response to the timing signal having the second value, operate in an isolation mode in which the switch isolation charge store is isolated from the power input.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.

Abstract: A temperature sensor arrangement (10), including a bandgap voltage generator (12), which is configured to provide an output voltage (Vbg); at least one semiconductor junction (14) for temperature sensing, which is biased by a biasing current flowing through said semiconductor junction (14); and at least one poly-resistor (Rb3) which is connected between the output (23) of the bandgap voltage generator (12) and the semiconductor junction (14), thereby providing said biasing current from the bandgap voltage generator (12) to the semiconductor junction (14).

Abstract: A communication system includes a transmission line and a reception coupler that couples to the transmission line in an electromagnetic field and moves along the transmission line, wherein the reception coupler has end parts narrower than other parts with respect to a transmission direction of the transmission line.