Abstract: UE, base station and data transmission method and apparatus. The method includes: in an unlicensed frequency band of 5G NR, a UE transmitting uplink data and associated UCI to a base station through AUL transmission; the base station identifying the UE through UE specific DMRS; the base station decoding the UCI; if the UCI is successfully decoded, the base station decoding the uplink data; based on whether a transport block or CBG is successfully decoded, the base station transmitting DFI to the UE, the DFI including first information used to indicate a location of the successfully decoded CBG; the UE receiving the DFI; the UE using the first information to determine HARQ-ID of a transport block where the CBG that needs to be retransmitted is located, and a sequence number of the CBG in a HARQ of the transport block where the CBG is located; the UE performing scheduling-free retransmission.

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: A data transmission method, apparatus, and system are applied to the field of communication technologies. The method includes: performing demultiplexing processing on obtained y first data streams to obtain x second data streams, where the y first data streams are obtained through bit multiplexing processing; mapping the x second data streams at a granularity of n bits to obtain z third data streams; and outputting the z third data streams over an output lane, where y, x, n, and z are all positive integers, and n?2. The method may be applied to an Ethernet high-speed interface.

Abstract: Provided is a system, an information processing method, and a non-transitory storage medium that hardly cause improper operations when a plurality of quantum processors is connected to configure a logical quantum bit.

Abstract: A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.

Abstract: A sign bit of a low-density parity-check (LDPC) codeword associated with a translation unit (TU) can be generated by performing an XOR operation on a RAIN drop corresponding to the TU and a raw read of the TU. The LDPC codeword can include a hard bit and three soft bits that include the sign bit. The LDPC codeword can be decoded using the hard bit and the three soft bits. A read recovery operation can be performed on the TU using the decoded LDPC codeword.

Abstract: Apparatuses, methods, and systems are disclosed for video codec aware RAN configuration and unequal error protection coding. An apparatus includes a processor that detects a video coded traffic stream and a video codec specification used to encode the video coded traffic stream, determines an awareness of video coded traffic application data units (“ADUs”) of the video coded traffic stream as video coded network abstraction layer (“NAL”) units of data, aligns the video coded NAL units of the video coded traffic stream to physical layer (“PHY”) transport elements and subsequent channel coding element partitions for a video coded traffic aware PHY transport, determines a channel coding rate allocation of the channel coding element partitions, and applies a forward error correction (“FEC”) coding given at least the determined channel coding rate allocation of the video coded traffic aware PHY transport to channel coding element partitions for protection against radio transmission errors.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to compare a first copy of a boot partition to a second copy of the boot partition. The first copy of the boot partition and the second copy of the boot partition each comprises a same number of a plurality of boot chunks. The boot partition corresponds to data of a boot operation of a host device. The controller is further configured to mark one or more of the compared boot chunks that equals or exceeds a similarity threshold and update a reliability index based on the marking. Based on the marking and the reliability index, the controller may increase or decrease an amount of error correction needed for the boot data.

Abstract: A method for coding (k, r) data and a method for reconstructing data are provided. The coding method includes steps consisting in: dividing an initial datum a into k data blocks ai; grouping the k data blocks into r?1 subsets Sj of data blocks; generating, for each subset Sj, a linear function gj(a) defined as a linear combination of the data blocks assigned to said subset Sj; and generating r parity functions comprising a primary parity function f0(a) as a linear combination of the k data blocks ai, and r?1 secondary parity functions, each secondary parity function fj(a) being defined as the sum of the primary parity function f0(a) and of a linear function gj(a).

Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured to optimize these different usage types upon detecting these proof of space blockchain activities. These optimizations can include suspending one or more background or other garbage collection activities. Additional optimizations can further include configuring partitions or namespaces to comprise single-level-cell majority or single-level-cell only memory devices to increase writing speeds. Further optimizations can include interleaving or extending the length of error correction codes.

Abstract: The present application provides a method and a system for calculating a stripe of a strip for a disk, a terminal and a storage medium. The method includes: calculating a pack offset of a parity block according to a given disk index; calculating an address of a strip where the parity block is located in the disk according to the pack offset; comparing an address of a to-be-checked strip with the address of the strip where the parity block is located in the disk to determine whether the parity block is on the to-be-checked strip; and calculating a stripe index of the to-be-checked strip by considering redundant elements caused by the parity block in response to determining that the parity block is on the to-be-checked strip; or calculating the stripe index of the to-be-checked strip directly in response to determining that the parity block is not on the to-be-checked strip.

Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.

Abstract: A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

Abstract: Methods, systems, and devices for configurable verify level are described. A host device may determine a target level of reliability for a set of data stored in a memory device. The host device may transmit, to the memory device, a command indicating the target level of reliability and a request to perform one or more error management operations for the set of data based on or in response to the target level of reliability. The memory device may determine the target level of reliability and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the set of data. The memory device may transmit, to the host device, an indication of a level of reliability of the set of data based on or in response to the command and performing the set of error management operations.

Abstract: A communication method includes obtaining a plurality of to-be-encoded symbols; determining, from a symbol matrix, a plurality of first symbols corresponding to the to-be-encoded symbols, where the symbol matrix includes a plurality of rows of symbols and a plurality of columns of symbols, symbols in the symbol matrix constitute a plurality of blocks, the blocks constitute a block matrix, and the first symbols include symbols in a plurality of first blocks in the block matrix, where the first blocks are grouped into at least one block group, a difference between row numbers of any two first blocks in any block group is not the same as a difference between row numbers of other two first blocks in the any block group; and performing check processing on the first symbols and the to-be-encoded symbols to generate checked symbols.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Abstract: A method of reading from a storage medium to recover a group of information sectors, each comprising a respective information payload. The medium stores redundancy data comprising a plurality of separate redundancy codes for the group, each code being a linear sum of terms, each term in the sum being the information payload from a different respective one of the information sectors in the group weighted by a respective coefficient of a set of coefficients for the redundancy code. The method comprises, after the redundancy data has already been stored on the medium: identifying a set of k? information sectors to be recovered; selecting k? of the redundancy codes; determining a square matrix E of the k? information sectors by the k? sets of coefficients of the selected codes; determining a matrix D being a matrix inverse of E; and recovering the k? information payloads from the inverse matrix D.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: An error correction encoding device includes an encoding unit to generate soft decision error correction frame information including a bit array of m rows and N columns obtained by combining first bit string group information and second bit string group information, the first bit string group information including a bit array of m rows and N1 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the first bit string group information into a modulation symbol by using a first symbol mapping rule, the second bit string group information including a bit array of m rows and N2 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the second bit string group information into a modulation symbol by using a second symbol mapping rule.