Abstract: A bit-flipping (BF) decoder and a decoding method based on a super node, which groups two or more component nodes corresponding to two or more bits in a codeword to generate a super node; and performs a decoding iteration on the super node. The decoding iteration includes: calculating a flipping energy for the super node based on a flipping energy for each of the component nodes and internal checks between the component nodes; and flipping at least one of the two or more bits in the super node upon a determination that the flipping energy for the super node exceeds a bit-flipping threshold.

Abstract: Various aspects of the present disclosure relate to video codec aware RAN configuration and unequal error protection coding. An apparatus includes a memory and a processor coupled to the memory that is configured to cause the apparatus to detect a video coded traffic stream and a video codec profile for encoding the video coded traffic stream, determine an awareness of PDU sets of the video coded traffic stream, align, based on at least the awareness of PDU sets, each PDU set of the video coded traffic stream to PHY transport elements and channel coding element partitions for a video coded traffic aware PHY transport, determine a channel coding rate allocation of the channel coding element partitions based on the video coded traffic aware PHY transport, and apply a FEC coding to the channel coding element partitions based in part on the channel coding rate allocation.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.

Abstract: A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

Abstract: Provided are a data processing system and method based on dynamic redundancy heterogeneous encoding, and a device. The method comprises: respectively performing error correction encoding on information to be processed and a processing rule, so as to form encoded information to be processed and an encoded processing rule; processing, by using the encoded processing rule, the encoded information to be processed, so as to obtain response data; and then performing error correction decoding on N pieces of response data, so as to obtain processing result information of the information to be processed.

Abstract: Applying Gottesman-Kitaev-Preskill (GKP) error correction to Gaussian input states, such as vacuum, produces distillable magic states, achieving universality without additional non-Gaussian elements. Gaussian operations are sufficient for fault-tolerant, universal quantum computing given a supply of GKP-encoded Pauli eigenstates.

Abstract: An information processing device includes an encoding processing unit and a determination unit. The encoding processing unit performs error correction encoding processing in which a plurality of bit sequences are output from one or more bit sequences. The determination unit divides the plurality of bit sequences into a first bit sequence group (BS1) and a second bit sequence group (BS2), and determines to transmit the first bit sequence group (BS1) and the second bit sequence group (BS2) through different propagation paths, the first bit sequence group (BS1) being decodable without performing error correction decoding processing corresponding to the error correction encoding processing, and the second bit sequence group (BS2) being used for the error correction decoding processing.

Abstract: Apparatus, methods, and computer program products for selecting an encoder for network coding are provided. An example method may include receiving one or more encoder information messages from a set of network coding devices, the one or more encoder information messages being associated with the set of network coding devices. The example method may further include transmitting a selection indication to at least one selected network coding device of the set of network coding devices, the selection indication indicating a selection of the at least one selected network coding device as an encoder for encoding at least one transport block (TB).

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: A storage device may execute a function of a data link layer among a plurality of communication layers of Unified protocol (UniPro), obtain a frame sequence number indicating a sequence of a first frame from the first frame before storing the first frame received from an external device into a reception buffer, and add the frame sequence number to a second frame.

Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is an extremely computationally intensive field such that performing artificial intelligence calculations can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence applications can be performed in parallel such that specialized linear algebra matrix processors can greatly increase computational performance. But even with linear algebra matrix processors; performance can be limited due to complex data dependencies. Without proper coordination, linear algebra matrix processors may end up idle or spending large amounts of time moving data around. Thus, this document discloses methods for efficiently scheduling linear algebra matrix processors.

Abstract: The present disclosure relates to a communication processing method and apparatus, and a storage medium. The communication processing method includes: in response to that a plurality of search spaces for repetition transmissions are configured in a same transmission time unit, performing detections in the search spaces for repetition transmissions according to a preset detection rule; and in response to that cumulative search spaces where the detections are performed exceed a physical downlink control channel detection limit, dropping a current search space where a detection is currently performed and a search space where a detection is not performed.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: Decoding method and memory system which group bits in irregular LDPC codes having similar degrees of convergence into respective degree groups, classify the degree groups according to a metric indicative of a number of decoding iterations for convergence, divide a time period for convergence of the decoding iterations into different zones for the processing of selected degree groups within each zone, and skip decoding of the bits in a non-converging zone where the bits are not converging.

Abstract: A deep learning-based MLCC stacked alignment inspection system includes an integrated defect detection unit configured to detect core areas requiring inspection of image data in which a stacked structure is photographed from a semiconductor MLCC chip by using at least one deep learning-based core area detection model, perform segmentation in the detected core areas, determine whether a defect exists according to a standard margin percentage range, and enable defect detection by generating normal and/or defective data based on the determination result, a result analysis unit configured to perform visualization for respective results of the core area detection, segmentation, and defect detection of the integrated defect detection unit, and provide stepwise analysis data for the visualized respective results so as to determine whether to modify corresponding data, and a data storage configured to store the normal and/or defective data, and stepwise analysis data.

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: A processing system operates by: detecting an access anomaly associated with an access request from a requestor for a set of encoded data slices, the access anomaly having an unfavorable access pattern, wherein the set of encoded data slices is dispersed storage error encoded and stored in at least one storage unit of the storage network; denying the access request in response to detecting the access anomaly; generating, based on the unfavorable access pattern, an anomaly detection indicator identifying the requestor; and sending the anomaly detection indicator to other devices of the storage network.

Abstract: In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.