Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

Abstract: A method for execution by one or more computing devices includes selecting a first routing path from a plurality of routing paths to a set of storage units based on routing path performance information, where the first routing path has a performance level greater than a first performance threshold. The method further includes selecting a second routing path from the plurality of routing paths based on the routing path performance information, where the second routing path has a performance level less than or equal to the first performance threshold. The method further includes sending a first subset of encoded data slices to the set of storage units via the first routing path for storage therein. The method further includes sending a second subset of encoded data slices to the set of storage units via the second routing path for storage therein.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.

Abstract: In a data transmission method, a first chip receives a first data stream sent by a second chip, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type; and the first chip encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.

Abstract: A method for execution by one or more processing modules of a storage network begins by receiving an access request for a set of encoded data slices, where the data object is segmented into a plurality of data segments, a data segment of which is dispersed error encoded in accordance with dispersed error encoding parameters to produce the set of encoded data slices. The method continues by determining whether a revision for one or more encoded data slices in a first storage module is a most recent revision level for the one or more encoded data slices and when the one or more encoded data slices is a most recent revision level, determining whether the revision level for the one or more encoded data slices in a second storage module is the most recent revision level.

Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a first device may combine, for each of a set of sub-blocks of a block of data, a set of unencoded bits associated with a respective sub-block with a matrix to generate a set of encoded bits. The first device may transmit a first message including the block to a second device. The second device may determine respective probabilities of successful decoding of respective selected candidate codewords for the set of sub-blocks of the block based on receiving the first message and may transmit one or more indicators associated with one or more sub-blocks based on the respective probabilities of successful decoding of the respective selected candidate codewords. The first device may transmit a second message including redundancy information for the one or more sub-blocks based on transmitting the one or more indicators.

Abstract: A method includes: a first chip receives a first data stream from a second chip, where the first data stream is obtained through encoding by using a first forward error correction (FEC) code type; and the first chip re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

Abstract: An infrastructure equipment that transmits signals representing data via a wireless access interface to a communications device and receives signals representing data via the wireless access interface from the communications device in accordance with a time divided structure in which the wireless access interface is divided into a plurality of repeating time units. The infrastructure equipment provides, in each of a first plurality of the time units, one of a plurality of control channels each configured to schedule one of a plurality of data channels, and provides, in each of a second plurality of time units of the signal transmitted to the communications device, one of the plurality of data channels, the plurality of data channels being formed of one or more bundles of data channels, wherein the infrastructure equipment transmits a bundle status indicator in one or more of the plurality of control channels.

Abstract: An encoding method includes obtaining to-be-encoded information and a mother code length N. The to-be-encoded information includes K information bits. The method also includes determining, based on K and N, a set I corresponding to subchannels of the information bits and a set F corresponding to subchannels of frozen bits. Information bits corresponding to subchannel sequence numbers in the set I are distributed in X outer component codes, a code length of each outer component code is B, and the X outer component codes includes a first-type outer component code and a second-type outer component code or the X outer component codes include a first-type outer component code, a second-type outer component code, and one third-type outer component code. Different types of component codes have different code rates. The method additionally includes performing polarization encoding based on the set I and the set F.

Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

Abstract: Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

Abstract: The present disclosure relates to stripe management methods, storage systems, stripe management apparatuses, and storage mediums. In one example method, check units in a plurality of stripes are obtained. A first stripe of the plurality of stripes complies with a first erasure code ratio. A new check unit is generated based on the check units in the plurality of stripes. The new check unit and data units in the plurality of stripes belong to a new stripe, the new stripe complies with a second erasure code ratio, and a quantity of data units corresponding to the first erasure code ratio is less than a quantity of data units corresponding to the second erasure code ratio.

Abstract: Decoding method and memory system that classify check nodes in a matrix having irregular check node weights into different groups according to the check node weights, apply different scaling factors to respective constant node to variable node (C2V) messages in the different groups of the check nodes, and optionally add a compensation term to at least one of the C2V messages of the MS decoder.

Abstract: Embodiments of the present disclosure disclose obtaining to-be-encoded first information that includes first and second information bit sets. The bits included in the first information bit set are obtained through decoding by a plurality of terminal devices. The bits included in the second information bit set are able to be obtained through decoding by some of the plurality of terminal devices. Polar encoding is first performed on the first information bit set to obtain first encoded information. Polar encoding is then performed on the second information bit set based on the first encoded information to obtain second encoded information.

Abstract: A method for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error correcting code (ECC) as first encoded data, wherein the ECC is configured to have a minimum Hamming distance of at least 4t+1 in order to correct up to t bit errors and detect up to 3t bit errors where t?1; determining a Hamming weight of the first encoded data; encoding the determined Hamming weight, wherein for all higher Hamming weights the encoding should have at least 2t+1 bit-positions that change from 1 to 0 per Hamming weight; concatenating the first encoded data and the encoded Hamming weight as concatenated data; and storing the concatenated data in the memory.

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q?1)?n.