Abstract: A storage device may execute a function of a data link layer among a plurality of communication layers of Unified protocol (UniPro), obtain a frame sequence number indicating a sequence of a first frame from the first frame before storing the first frame received from an external device into a reception buffer, and add the frame sequence number to a second frame.

Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

Abstract: Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is an extremely computationally intensive field such that performing artificial intelligence calculations can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence applications can be performed in parallel such that specialized linear algebra matrix processors can greatly increase computational performance. But even with linear algebra matrix processors; performance can be limited due to complex data dependencies. Without proper coordination, linear algebra matrix processors may end up idle or spending large amounts of time moving data around. Thus, this document discloses methods for efficiently scheduling linear algebra matrix processors.

Abstract: The present disclosure relates to a communication processing method and apparatus, and a storage medium. The communication processing method includes: in response to that a plurality of search spaces for repetition transmissions are configured in a same transmission time unit, performing detections in the search spaces for repetition transmissions according to a preset detection rule; and in response to that cumulative search spaces where the detections are performed exceed a physical downlink control channel detection limit, dropping a current search space where a detection is currently performed and a search space where a detection is not performed.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: A deep learning-based MLCC stacked alignment inspection system includes an integrated defect detection unit configured to detect core areas requiring inspection of image data in which a stacked structure is photographed from a semiconductor MLCC chip by using at least one deep learning-based core area detection model, perform segmentation in the detected core areas, determine whether a defect exists according to a standard margin percentage range, and enable defect detection by generating normal and/or defective data based on the determination result, a result analysis unit configured to perform visualization for respective results of the core area detection, segmentation, and defect detection of the integrated defect detection unit, and provide stepwise analysis data for the visualized respective results so as to determine whether to modify corresponding data, and a data storage configured to store the normal and/or defective data, and stepwise analysis data.

Abstract: Decoding method and memory system which group bits in irregular LDPC codes having similar degrees of convergence into respective degree groups, classify the degree groups according to a metric indicative of a number of decoding iterations for convergence, divide a time period for convergence of the decoding iterations into different zones for the processing of selected degree groups within each zone, and skip decoding of the bits in a non-converging zone where the bits are not converging.

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.

Abstract: A processing system operates by: detecting an access anomaly associated with an access request from a requestor for a set of encoded data slices, the access anomaly having an unfavorable access pattern, wherein the set of encoded data slices is dispersed storage error encoded and stored in at least one storage unit of the storage network; denying the access request in response to detecting the access anomaly; generating, based on the unfavorable access pattern, an anomaly detection indicator identifying the requestor; and sending the anomaly detection indicator to other devices of the storage network.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: A method for execution by one or more computing devices includes selecting a first routing path from a plurality of routing paths to a set of storage units based on routing path performance information, where the first routing path has a performance level greater than a first performance threshold. The method further includes selecting a second routing path from the plurality of routing paths based on the routing path performance information, where the second routing path has a performance level less than or equal to the first performance threshold. The method further includes sending a first subset of encoded data slices to the set of storage units via the first routing path for storage therein. The method further includes sending a second subset of encoded data slices to the set of storage units via the second routing path for storage therein.

Abstract: In a data transmission method, a first chip receives a first data stream sent by a second chip, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type; and the first chip encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.

Abstract: A method for execution by one or more processing modules of a storage network begins by receiving an access request for a set of encoded data slices, where the data object is segmented into a plurality of data segments, a data segment of which is dispersed error encoded in accordance with dispersed error encoding parameters to produce the set of encoded data slices. The method continues by determining whether a revision for one or more encoded data slices in a first storage module is a most recent revision level for the one or more encoded data slices and when the one or more encoded data slices is a most recent revision level, determining whether the revision level for the one or more encoded data slices in a second storage module is the most recent revision level.

Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a first device may combine, for each of a set of sub-blocks of a block of data, a set of unencoded bits associated with a respective sub-block with a matrix to generate a set of encoded bits. The first device may transmit a first message including the block to a second device. The second device may determine respective probabilities of successful decoding of respective selected candidate codewords for the set of sub-blocks of the block based on receiving the first message and may transmit one or more indicators associated with one or more sub-blocks based on the respective probabilities of successful decoding of the respective selected candidate codewords. The first device may transmit a second message including redundancy information for the one or more sub-blocks based on transmitting the one or more indicators.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.

Abstract: A method includes: a first chip receives a first data stream from a second chip, where the first data stream is obtained through encoding by using a first forward error correction (FEC) code type; and the first chip re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.