Abstract: An encoding method includes obtaining to-be-encoded information and a mother code length N. The to-be-encoded information includes K information bits. The method also includes determining, based on K and N, a set I corresponding to subchannels of the information bits and a set F corresponding to subchannels of frozen bits. Information bits corresponding to subchannel sequence numbers in the set I are distributed in X outer component codes, a code length of each outer component code is B, and the X outer component codes includes a first-type outer component code and a second-type outer component code or the X outer component codes include a first-type outer component code, a second-type outer component code, and one third-type outer component code. Different types of component codes have different code rates. The method additionally includes performing polarization encoding based on the set I and the set F.

Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

Abstract: Decoding method and memory system that classify check nodes in a matrix having irregular check node weights into different groups according to the check node weights, apply different scaling factors to respective constant node to variable node (C2V) messages in the different groups of the check nodes, and optionally add a compensation term to at least one of the C2V messages of the MS decoder.

Abstract: The present disclosure relates to stripe management methods, storage systems, stripe management apparatuses, and storage mediums. In one example method, check units in a plurality of stripes are obtained. A first stripe of the plurality of stripes complies with a first erasure code ratio. A new check unit is generated based on the check units in the plurality of stripes. The new check unit and data units in the plurality of stripes belong to a new stripe, the new stripe complies with a second erasure code ratio, and a quantity of data units corresponding to the first erasure code ratio is less than a quantity of data units corresponding to the second erasure code ratio.

Abstract: Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

Abstract: Embodiments of the present disclosure disclose obtaining to-be-encoded first information that includes first and second information bit sets. The bits included in the first information bit set are obtained through decoding by a plurality of terminal devices. The bits included in the second information bit set are able to be obtained through decoding by some of the plurality of terminal devices. Polar encoding is first performed on the first information bit set to obtain first encoded information. Polar encoding is then performed on the second information bit set based on the first encoded information to obtain second encoded information.

Abstract: A method for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error correcting code (ECC) as first encoded data, wherein the ECC is configured to have a minimum Hamming distance of at least 4t+1 in order to correct up to t bit errors and detect up to 3t bit errors where t?1; determining a Hamming weight of the first encoded data; encoding the determined Hamming weight, wherein for all higher Hamming weights the encoding should have at least 2t+1 bit-positions that change from 1 to 0 per Hamming weight; concatenating the first encoded data and the encoded Hamming weight as concatenated data; and storing the concatenated data in the memory.

Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q?1)?n.

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract: Incoming sensor data from a data collection device may be received at the data processing platform that includes the plurality of data processing microservices. A data processing microservice of the data processing platform may detect that the incoming sensor data from the data collection device caused an error. As a result, the incoming sensor data may be queued in a faulty data cache of the data processing platform. Subsequently, at least one of the data processing microservice or the incoming sensor data stored in the faulty data cache may be modified such that the incoming sensor data is processed by the data processing microservice without the error. Following the processing, the incoming sensor data may be deleted from the faulty data queue of the data processing platform.

Abstract: An electronic device is described that is configured to perform a series of low density parity check, LDPC, decoding operations that use at least one basegraph that comprises two or more columns, each column associated with a set of two or more soft bit values. The electronic device includes two or more rotators, each rotator configured to rotate an order of a subset of two or more soft bit values of the set of two or more soft bit values of a column when activated in an LDPC decoding operation; and wherein rotations associated with each column in each basegraph are performed by a particular one of the rotators of the two or more rotators, wherein each rotator performs rotations for a set of one or more columns, with at least one of the rotators performing rotations for two or more columns in a same basegraph.

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

Abstract: An audio transmitter processor for generating an error protected frame using encoded audio data of an audio frame, the encoded audio data for the audio frame having a first amount of information units and a second amount of information units, has: a frame builder for building a codeword frame having a codeword raster, wherein the frame builder is configured to determine a border between a first amount of information units and a second amount of information units so that a starting information unit of the second amount of information units coincides with a codeword border; and an error protection coder to obtain a plurality of processed codewords representing the error protected frame.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.

Abstract: The aspects described herein may enable an apparatus to jointly encode two or more payloads using a single polar encoder device, while providing unequal error protection for the payloads. The apparatus causes a polar encoder to polar encode a first payload and a second payload to generate a polar encoded codeword. The polar encoder is configured to encode one or more bits of the first payload at a first reliability level and encode one or more bits of the second payload at a second reliability level, where the one or more bits of the first payload are associated with a first priority level and the one or more bits of the second payload are associated with a second priority level. The apparatus transmits the polar encoded codeword.

Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

Abstract: Forward Error Correction decoding is executed by acquiring a stream of real data symbols from a communication medium, the stream of real data symbols being arranged in a real matrix. Virtual data symbols are generated and arranged in a virtual matrix by applying an interleaver map onto the real matrix. Codewords formed by a main matrix formed by the real matrix and the virtual matrix are iteratively decoded, an iteration of the decoding comprising identifying a set of consecutive received rows of the main matrix, accessing a set of pre-determined reference codewords and in response to determining that a given codeword of the set of consecutive received rows does not match any pre-determined reference codewords, executing a GRAND algorithm on the given codeword, the GRAND algorithm generating a substitute codeword for the given codeword. A system comprising a processor and a memory executes the Forward Error Correction decoding.

Abstract: Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

Abstract: A method includes determining an information dispersal algorithm width number and determining a number of primary storage slots from a number of storage slots associated with a set of storage units deployed across multiple sites, where the number of primary storage slots is equal to or greater than the information dispersal algorithm width number. The method further includes determining a mapping of primary storage slots to storage units. The method further includes sending configuration information to the set of storage units that includes the mapping. The method further includes storing a set of encoded data slices in the primary storage slots in accordance with the configuration information, where a data segment is error encoded into the set of encoded data slices in accordance with the information dispersal algorithm width number and a decode threshold number, which is a number of encoded data slices are needed to reconstruct the data segment.