Abstract: An error correction encoding device includes an encoding unit to generate soft decision error correction frame information including a bit array of m rows and N columns obtained by combining first bit string group information and second bit string group information, the first bit string group information including a bit array of m rows and N1 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the first bit string group information into a modulation symbol by using a first symbol mapping rule, the second bit string group information including a bit array of m rows and N2 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the second bit string group information into a modulation symbol by using a second symbol mapping rule.

Abstract: A processing system operates by: storing a data segment as a set of encoded data slices, wherein the set of encoded data slices are dispersed storage error encoded and stored in at least one storage unit of a storage network; receiving, from a requestor, an access request associated with the data segment; detecting an access anomaly associated with the access request, the access anomaly having one of a plurality of anomaly types; denying the access request in response to detecting the access anomaly; generating, based on the one of the plurality of anomaly types, an anomaly detection indicator identifying the requestor; and sending the anomaly detection indicator to other devices of the storage network.

Abstract: A method includes dispersed storage error encoding a data object to produce a set of encoded data slices. The method further includes obtaining routing path performance information for a plurality of routing paths from the computing device to a set of storage units. The method further includes selecting a first routing path for sending a first subset of the set of encoded data slices, where the first routing path has a performance level greater than a first performance threshold. The method further includes selecting a second routing path for sending a second subset of the set of encoded data slices, where the second routing path has a performance level less than or equal to the first performance threshold. The method further includes sending the first and second subsets of encoded data slices to the set of storage units via the first and second routing paths for storage therein.

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: A method includes a network device receiving a plurality of fragments of an Ethernet frame, where the plurality of fragments include an initial fragment and a first fragment, and where the initial fragment includes a destination media access control (MAC) address field. In response to an error occurring in the Ethernet frame, the first fragment is changed to a second fragment, where the second fragment includes second type indication information (TII) and second to-be-transmitted data (TBTD), where the second TII indicates that a type of the second TBTD is a control character, where a value of first TBTD is different from a value of the second TBTD, and where the second TBTD indicates that an error occurs in the Ethernet frame. The network device sends the second fragment to a destination device.

Abstract: Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: Intelligent responses to errors in a storage system, including: after a first attempt to read data from a first set of resources in a storage system results in an error, determining whether to issue a second attempt to read data from the first set of resources in a storage system; responsive to determining not to issue the second attempt to read data from the first set of resources in a storage system, retrieving the data from a second set of resources in the storage system; and responsive to determining to issue the second attempt to read data from the first set of resources in a storage system, issuing a second read attempt to read the data, wherein the error correction effort level associated with the second attempt is increased relative to the error correction effort level associated with the first attempt.

Abstract: An apparatus may be configured to receive a polar-encoded transmission comprising at least one intermediate node associated with a first configuration of frozen leaf nodes and information leaf nodes. The apparatus may further be configured to apply an FHT to a first set of values associated with a first intermediate node of the at least one intermediate node to generate a second set of values associated with the first intermediate node. The apparatus may also be configured to select, based on the second set of values, one or more paths associated with the first intermediate node for a SSCL decoding. The apparatus may further be configured to calculate a path metric for each of the selected one or more paths associated with the first intermediate node.

Abstract: Disclosed are an apparatus and method for successive cancellation flip decoding of a polar code. The apparatus for successive cancellation flip decoding of a polar code according to an embodiment includes an iterative unit subtotal matrix generator configured to generate an iterative unit subtotal matrix corresponding to a preset iterative unit size based on a portion of an entire subtotal matrix, a selection logic configured to determine one or more selection bits based on a bit string representing a position of a bit returned when re-decoding and generate an auxiliary matrix for generating the entire subtotal matrix from the one or more selection bits, and an entire subtotal matrix generator configured to generate the entire subtotal matrix by using the iterative unit subtotal matrix and the auxiliary matrix.

Abstract: This application relates to the field of communication technologies, and discloses a polar coding/decoding method and apparatus, to improve sequence lookup efficiency. The method includes: obtaining a first sequence from a polar code construction sequence table based on a coding parameter, where the polar code construction sequence table includes at least one coding parameter and at least one sequence corresponding to the at least one coding parameter, the coding parameter is mapped to the sequence in a one-to-one manner, the first sequence is one of the at least one sequence; and selecting serial numbers of K polarized channels from the first sequence based on a rate matching scheme and/or a reliability order, placing to-be-coded bits based on the selected serial numbers of the K polarized channels, and performing polar coding, to obtain a coded bit sequence.

Abstract: A method for channel encoding in a communication or broadcasting system is provided. The method includes determining a block size Z, and performing encoding based on the block size and a first matrix corresponding to the block size, wherein the first matrix is determined based on information and a plurality of second matrices, and wherein a part of a column index indicating a position of a non-zero element in each row of the information includes an index according to mathematical expression 22 above.

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q?1)?n.

Abstract: Techniques for using data mirroring across regions to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload first and second copies of a data object to first and second regions of the cloud object storage platform respectively, where the first and second copies are identical. The computer system can then attempt to read the first copy of the data object from the first region. If the read attempt fails, the computer system can retrieve the second copy of the data object from the second region.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

Abstract: A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.

Abstract: A method of decoding a polar coded signal includes determining channel reliabilities for a plurality of polar coded bit channels in a data communication system including a plurality of frozen bit channels and non-frozen bit channels, selecting a frozen bit channel, calculating a likelihood value for a bit estimate associated with the frozen bit channel, generating a hard decision value for the bit estimate in response to the likelihood value, comparing the hard decision value for the bit estimate to a known value of a frozen bit transmitted on the frozen bit channel, in response to determining that the hard decision value for the bit estimate differs from the known value of the frozen bit transmitted on the frozen bit channel, updating an accumulated uncertainty, comparing the accumulated uncertainty to a threshold, and determining that a decoding error has occurred in response to the comparison.