Patents Examined by Kalpit Parikh
  • Patent number: 11126359
    Abstract: Inventive aspects include a method, apparatus, and system for partitioning and processing graph data for large-scale graphs. Such may include, in a partitioning pre-processing step, assigning a plurality of destination vertices to a plurality of partitions such that each destination vertex of the plurality of destination vertices is uniquely assigned to only one partition from among the plurality of partitions. Such may also include, in a main execution of external graph processing step, (i) loading a given partition of destination vertices from among the plurality of partitions from a solid state drive (SSD) into a main memory of a computing machine, (ii) streaming one or more chunks of source vertex data from the SSD into the main memory of the computing machine, and (iii) performing graph processing based at least on the loaded given partition of destination vertices and the streamed one or more chunks of source vertex data.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 21, 2021
    Inventors: Nima Elyasi, Changho Choi
  • Patent number: 11126553
    Abstract: Techniques are presented for dynamically allocating memory between containers.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 21, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Sudhir Srinivasan
  • Patent number: 11119654
    Abstract: Provided are a computer program product, system, and method for determining an optimal storage environment for data sets and for migrating data sets. Metadata for each application indicates storage pools used by the application to store data sets, wherein each storage pool is configured in one of a plurality of storage environments using different organization schemes to store data sets. The metadata for at least one application indicates storage pools to store the data sets for the application that are allocated from different storage environments. The metadata for an application is processed to determine a data set for the application stored in a first storage pool implemented in a first storage environment that should be stored in a second storage environment. The determined data set from the first storage pool to a second storage pool implemented in the second storage environment.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clea A. Zolotow, Thomas W. Bish, Bernhard J. Klingenberg, Petra Kopp, John V. Delaney
  • Patent number: 11112985
    Abstract: Techniques for processing data may include: receiving a candidate data block; computing a distance using a distance function, wherein the distance denotes a measurement of similarity between the candidate data block and a target data block; and determining, using the distance, whether to perform data deduplication of the candidate data block with respect to the target data block to identify at least one sub-block of the candidate data block that is a duplicate of at least one sub-block of the target data block. The distance may be computed using a bit-wise logical exclusive-or operation of the contents of the candidate data block and the target data block. The distance may be computed using a bit-wise logical exclusive-or operation of digests computed for the candidate and target data blocks using a distance preserving hash function. The target and candidate block may be similar if the distance is less than a threshold.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 7, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Ivan Bassov, Philippe Armangau, Sorin Faibish, Istvan Gonczi
  • Patent number: 11093382
    Abstract: Methods and systems are provided for compression and reconstruction of system data. A controller of a memory system includes a compression component for searching for a pattern of an array of system data including a plurality of elements and compressing the array of system data based on the pattern. The array of system data includes neighbor elements corresponding to a first pattern, among the plurality of elements. The compressed system data includes: first information including a first bit indicating a first content; and second information including a first bitmap, each bit of the first bitmap indicating whether a corresponding element is a first element among the neighbor elements of the first pattern.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Igor Novogran, Alexander Ivaniuk
  • Patent number: 11086787
    Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Bryan Lloyd
  • Patent number: 11074199
    Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 27, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: David F. Heinrich, Theodore F. Emerson, Don A. Dykes, Sukhamoy Som
  • Patent number: 11074194
    Abstract: Managing direct memory access (DMA) by: defining a translate control entity (TCE) cache flag for cache memory addresses, receiving a DMA TCE related request, checking the TCE cache flag status, and completing the TCE related request according to the TCE cache flag status.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sakethan Reddy Kotta, Eric Norman Lais, Rama Krishna Hazari, Kumaraswamy Sripathy
  • Patent number: 11074011
    Abstract: A solid state drive system and method receives read commands, write commands, and/or file system updates. The solid state drive system then determines the latency estimate for performing each of those commands asynchronously. The solid state drive system may utilize internal processes to determine the latency estimate. The latency estimate may include random access latency, block erase time, outstanding workload latency, garbage collection time, metadata write time, etc. The latency estimate is then returned to the host device. The host device may utilize the latency estimate to workload balance solid state drive systems.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11074179
    Abstract: A method for managing objects stored in memory is presented. The method may include receiving, by a memory allocator in a garbage collected system, a first free memory chunk. The method may include creating a node to associate with the first free memory chunk and ensuring that a first memory region containing the node will be considered to be free memory during a sweeping phase of the garbage collected system.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 27, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Lokesh Gidra, Evan R Kirshenbaum
  • Patent number: 11073997
    Abstract: Provided is a storage system and a data management method of a storage system enabling system-wide data deduplication. The storage system has a plurality of storage apparatuses in which one or a plurality of logical volumes are provided. Based on data information of data obtained through the generation of a request to write to a logical volume in the storage system, one storage apparatus among the plurality of storage apparatuses calculates, for a plurality of combinations of storage apparatus and logical volume in the storage system, a data capacity when duplicate data is removed for each of the storage apparatuses, calculates the total of the calculated data capacities as the total capacity of the whole storage system, and performs optimal arrangement arithmetic processing to output information indicating a combination with the smallest total capacity among the plurality of combinations.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Yoshio Sonokawa, Yuki Kuroda, Hirokazu Ogasawara, Kozue Fujii
  • Patent number: 11061580
    Abstract: A storage device includes a plurality of flash memories, a first local controller connected to a first group of flash memories among the plurality of flash memories, a second local controller connected to a second group of flash memories among the plurality of flash memories, and a global controller. The global controller transmits commands to the first local controller and the second local controller. The first local controller includes a first processor that transmits first information on a type and number of commands associated with an operation performed on the first group of flash memories to the global controller. The second local controller includes a second processor that transmits second information on a type and number of commands associated with an operation performed on the second group of flash memories to the global controller.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Woong Kim, Nam Wook Kang, Da Woon Jung
  • Patent number: 11061865
    Abstract: An LL server (LLS) may process metadata requests for a file system in LL mode in a distributed file storage services (DFSS). For requests that require allocating blocks to file system objects in the backing store, instead of relying on distributed transactions used for file systems in high throughput (HT) mode, a pool of blocks may be pre-allocated for the LL file system in the backing store, and a free block list may be maintained in local memory of the LLS. When a metadata operation requires blocks to be allocated, the blocks are assigned to the respective object from the blocks in the pool. A background process may allocate new blocks in the pool upon the number of blocks dropping below a threshold, or upon block allocation rate for the file system increasing.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jacob A. Strauss, Michael Robert Frasca, Neal John Charbonneau
  • Patent number: 11055028
    Abstract: A processing device is configured to receive a plurality of input-output requests in a storage system, the input-output requests comprising read requests and write requests, to determine priorities of respective ones of the read requests, to place one or more of the read requests each having a relatively low priority in a first one of a plurality of queues in one of a plurality of processing cores of the storage system, to place one or more of the read requests each having a relatively high priority in a second one of the plurality of queues in the processing core, and to place the write requests in the first queue. The storage system services the read requests and the write requests from their corresponding ones of the first and second queues, illustratively resulting in reduced read latency for one or more relatively high priority read requests placed in the second queue.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: July 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Amitai Alkalay
  • Patent number: 11048411
    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a flash memory to store data and support for a number of device streams. The SSD may also include an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a host interface logic, which may include a receiver to receive the commands associated with software streams from a host, a timer to time a window, a statistics collector to determine values for at least one criterion for the software streams from the commands, a ranker to rank the software streams according to the values, and a mapper to establish a mapping between the software streams and device streams.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 29, 2021
    Inventors: Hingkwan Huen, Changho Choi
  • Patent number: 11029849
    Abstract: Provided are techniques for handling cache and Non-Volatile Storage (NVS) out of sync writes. At an end of a write for a cache track of a cache node, a cache node uses cache write statistics for the cache track of the cache node and Non-Volatile Storage (NVS) write statistics for a corresponding NVS track of an NVS node to determine that writes to the cache track and to the corresponding NVS track are out of sync. The cache node sets an out of sync indicator in a cache data control block for the cache track. The cache node sends a message to the NVS node to set an out of sync indicator in an NVS data control block for the corresponding NVS track. The cache node sets the cache track as pinned non-retryable due to the write being out of sync and reports possible data loss to error logs.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Beth A. Peterson
  • Patent number: 11030092
    Abstract: An access request processing apparatus comprises, a processor determines an object cache page according to a write request when receiving the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 8, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Xu, Qun Yu, Licheng Chen
  • Patent number: 11010066
    Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel
  • Patent number: 10996867
    Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jianmin Huang, Kulachet Tanpairoj, Harish Reddy Singidi, Ting Luo
  • Patent number: 10977176
    Abstract: A first memory request including a first virtual address is received. An entry in memory is accessed. The entry is selected using information associated with the first memory request, and includes at least a portion of a second virtual address (first data) and at least a portion of a third virtual address (second data). The difference between the first data and the second data is compared with differences between a corresponding portion of the first virtual address and the first data and the second data respectively. When a result of the comparison is true, then a fourth virtual address is determined by adding the difference between the first data and the second data to the first virtual address, and then data at the fourth virtual address is prefetched into the cache.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 13, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: David Carlson, Shubhendu S. Mukherjee