Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.

Abstract: A processing-in-memory (PIM) device including a data storage region, a global buffer and an arithmetic circuit. The data storage region configured to store vector data and weight data. The global buffer configured to store vector data read from the data storage region. The arithmetic circuit configured to generate a calculation result by performing a calculation on vector data read from the global buffer and weight data read from the data storage region.

Abstract: Write removal for solid-state drives can be managed. For example, a computing device can designate a space of a solid-state drive (SSD) for a write of container. The computing device can store the write for the container in the space in response to loading the container for executing the container. The computing device can determine an end to an execution phase for the container. In response to determining the end to the execution phase, the computing device can remove the write from the space of the SSD.

Abstract: The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

Abstract: A first request to initiate a memory access transaction is received by a processing device of a memory sub-system from a host system. One or more host data items are received from the host system. The one or more host data items are stored in a memory buffer residing on a volatile memory device of the memory sub-system. In response to an initiation of one or more operations to commit the memory access transaction, the one or more data items are migrated from the memory buffer to a persistent memory device.

Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: In a multi-tiered system, a read temperature classification and write temperature classification per virtual block (VLB) can be determined based on the content referenced by each VLB. The temperature classifications of VLBs can be determined using temperature scales which map read and write activity levels to corresponding temperature classifications. The temperature scales can have classification boundaries adjusted based on feedback of operations performed including down-tiering, garbage collection, and compaction and appending. In one use case, a number of free blocks in a high-performance first tier can be below a minimum and processing can be performed to locate a source block of the first tier partially filled with hot content, store the hot content contiguously on a target block of the first tier, flush write data from a log, and store the write data on the target block by appending the write data to the existing hot content.

Abstract: A data access method and apparatus and a storage medium are disclosed. In an embodiment, a storage device receives from a client a first data write request that includes target data to be written and an address of a service logical space corresponding to the target data; and determines, based on an address of the service logical space, a target hard disk in the storage device and an address of a hard disk logical space corresponding to the service logical space. The storage device further writes the target data into the target hard disk based on the address of the hard disk logical space.

Abstract: A task generator runs on a data storage system in which multiple compute nodes allocate portions of local memory to a remotely accessible shared memory. The task generator is responsive to a primary task to be performed on a storage object to generate separate, per-compute node secondary tasks corresponding to the primary task. Each of the separate secondary tasks specifies at least one attribute of metadata associated with the storage object and at least one task logic function. Each of the plurality of compute nodes performs the separate secondary task generated for that compute node by scanning the local portion of the shared memory based on the attribute to identify matching pages of the metadata associated with the storage object and performs the task logic function on the identified matching pages of the metadata associated with the storage object to generate a local result. The task generator combines the local results to perform the primary task.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a current access request for a storage media associated with a stream, identify a hint in the current access request which indicates one or more stream characteristics for future access requests from the stream, and handle the current access request based on the indicated one or more stream characteristics for future access requests from the stream. Other embodiments are disclosed and claimed.

Abstract: Technologies are described herein for remotely configuring multi-mode dual in-line memory modules (“multi-mode DIMMs”) using a firmware or a baseboard management controller (“BMC”). Technologies are also described for simultaneously initiating multiple commands for configuring multi-mode DIMMs using a BMC and for updating inventory data regarding multi-mode DIMMs stored by a BMC.

Abstract: A processing device in a memory system determines that a number of commands from an active queue that have been executed on a memory device does not satisfy an executed transaction threshold criterion, that a number of pending commands in an inactive queue satisfies a first promotion threshold criterion, and that a number of pending commands in the active queue does not satisfy a second promotion threshold criterion. In response, the processing device switches an execution grant from the active queue to the inactive queue.

Abstract: A method for accessing a flash memory module includes: determining a type of data to be written into the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to the type of data, wherein the plurality of sets of encoding/decoding settings correspond to different data lengths, respectively; utilizing the specific encoding/decoding setting to encode the data to generate encoded data; and writing the encoded data into a block of the flash memory module.

Abstract: A processing device in a memory sub-system generates a fill operation to store data from a memory device at a cache of a memory sub-system, assigns a first priority indicator to the fill operation associated with the data, and assigns a second priority indicator to a read operation associated with a request to read the data from the memory sub-system. The processing device further determines a schedule of executing the fill operation and the read operation based on the first priority indicator and the second priority indicator and executes the fill operation and the read operation based on the determined schedule.

Abstract: A memory controller controls access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks. The memory controller includes: a receiver that receives a memory access request from an access master; a selector that selects one of a first issue mode and a second issue mode each related to command issuing; and an issuer that issues a command sequence to the SDRAM in response to the memory access request, in accordance with the one of the first issue mode and the second issue mode which is selected by the selector. The first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence. The second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles.

Abstract: Systems, apparatus and methods are provided for power management of non-volatile storage (NVM) systems. A non-volatile storage system may include a first interface to be coupled to a host, a NVM device, a storage controller including a command queue and a processor, and a second interface coupling the storage controller and the NVM device. The processor may be configured to handle data transfer requests from the host in an active power state, monitor the command queue and a data transfer rate on the first interface, determine that the data transfer rate falls below a predetermined threshold and the command queue is empty, enter a pseudo-idle power state, determine that there is a new command from the host, and exit the pseudo-idle power state and enter the active power state.

Abstract: In the case of FC-NVMe (NVMe over Fabrics using Fibre Channel (FC) as a transport), zoning is typically performed using the interface WWPNs, but the masking of NVMe namespaces is performed using a host's NVMe Qualified Name (NQN or HOSTNQN). The use of two identifiers (i.e., one identifier used for zoning and another identifier used for masking) introduces a potential security related concern. A bad actor may obtain the NQN of a host that has access to sensitive information and use it to access this sensitive information. Accordingly, in one or more embodiments, by correlating different identifiers and using a combination of the different identifiers, access can easily be provided to the appropriate host adapters while prohibiting access to rogue hosts.

Abstract: Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.