Abstract: A multiple function storage device is disclosed. The multiple function storage device may include an enclosure, a storage device associated with the enclosure, and an bridging device associated with the enclosure. The storage device may include a connector to receive a first message using a first protocol originating at a host, a physical function (PF) and a virtual function (VF) exposed by the storage device via the connector, storage for data relating to the first message, and a controller to manage writing a write data to the storage and reading a read data from the storage.

Abstract: A method, apparatus, and system for processing Redundant Array of Independent Disks (RAID) Input/Output (I/O) requests for a plurality of nodes in a cluster is disclosed. A file system request including a byte offset is received. Then, a Physical Extent (PE) row that matches the file system request and a RAID stripe within the identified PE row based on the byte offset is identified. Next, a plurality of RAID I/O requests to be routed to a physical disk is generated. Each of the plurality of the RAID I/O requests includes information associated with the PE and a type of operation. Thereafter, each of the RAID I/O requests is processed based on the information associated with the PE and the type of operation.

Abstract: A method performed by a controller of an SSD, the controller coupled to a non-volatile semiconductor memory device and comprising a first command queue (Q1) and a second command queue (Q2). The method comprises selecting from a submission queue at least one command from a host, the command relating to an action to be performed on the memory device. The method comprises determining if a number of in-flight commands received from the host via the submission queue and already present in Q1 exceeds a threshold. The method comprises adding the selected command to Q2 if the threshold is exceeded, otherwise adding the selected command to Q1. The method comprises processing a first command from Q1 and a second command from Q2 to perform a first action and a second action, respectively, on the memory device, the first action being completed in advance of the second action.

Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

Abstract: A method and apparatus for performing resuming management are provided. The method includes: utilizing a boot loader to load a group of In-System Programming (ISP) codes; storing information to be retained, including a resume ISP loader, into a retention region of a RAM, for being retained during sleeping; determining whether to start sleeping, and generating a determining result; in response to the determining result, controlling the memory device to start sleeping; after starting sleeping, determining whether a wake-up event occurs; after the wake-up event occurs, executing a first ISP code within the group of ISP codes to start performing a first operation; and executing the resume ISP loader to load other ISP codes within the group of ISP codes.

Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.

Abstract: A storage device includes a nonvolatile memory device that includes a first region including memory cells configured to store n-bit data and a second region including memory cells configured to store m-bit data and a memory controller, where n and m are natural numbers and n is less than m. The first region includes a first area and a second area, and the second region includes a third area. The memory controller is configured to perform one of a turbo write operation on the first area or the second area and a normal write operation on the third area, and configured to perform one of a turbo read operation on the first area or the second area and a normal read operation on the third area.

Abstract: Aspects of a storage device including at least one die and a controller are provided that allow superblock formation using surplus block pairs when bad blocks occur. After the controller forms a superblock including a first block in a first plane of the die and a second block in a second plane of the die, the controller identifies the first block as a bad block and switches the second block into a surplus state (or vice-versa). The controller then forms a new superblock from blocks in a spare pool. When the number of blocks is equal to a superblock threshold, the controller attempts to pair the surplus block with another surplus block from the opposite plane according to a die sequence. If the attempt to pair is successful, the controller adds the pair to the spare pool; otherwise, the surplus block is not added to the spare pool.

Abstract: Aspects of the present disclosure relate to a method of writing a dataset to a tape, the dataset comprising a plurality of sub datasets, each sub dataset including a plurality of headers and a plurality of records. The method includes storing, in each header of each sub dataset, at least a portion of a record range indicator indicating a range of records included in the dataset.

Abstract: Systems, methods and apparatus of communications with a data storage device in neural network computations. For example, a vehicle can have a set of sensors configured to generate a sensor data stream for predictive Maintenance. One or more processors of the vehicle generates inputs to artificial neurons based on the sensor data. The inputs are written into the data storage device, which is configured with a neural network accelerator and stores model data of an artificial neural network (ANN). The neural network accelerator applies the inputs to the ANN to generate outputs. The data storage device reports the availability of the outputs (e.g., using a response to the request to write the inputs into the data storage device). The processor(s) of the vehicle can selectively read the outputs from the data storage device and/or request the data storage device to store the outputs from buffer to non-volatile memory.

Abstract: A data storage device configured to access a magnetic tape comprising a plurality of data tracks is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A mapping table is generated having a predetermined number of segment entries per data track, wherein each segment entry corresponds to a data segment of the data track, each segment entry comprises a first logical address corresponding to a first logical data block stored in the corresponding data segment, and at least one of the data segments stores multiple logical data blocks. A target segment entry in the mapping table corresponding to a logical address of a read command is located, and the head is positioned at a beginning of a target data segment of a target data track corresponding to the target segment entry in order to execute the read command.

Abstract: Systems, methods and apparatus of optimizing neural network computations of predictive maintenance of vehicles. For example, a data storage device of a vehicle includes: a host interface configured to receive a sensor data stream from at least one sensor configured on the vehicle; at least one storage media component having a non-volatile memory; and a controller. The non-volatile memory is configured into multiple partitions (e.g., namespaces) having different sets of memory operation settings configured for different types of data related to an artificial neural network (ANN). The partitions include an input partition configured to store input data to the ANN. The sensor data stream is applied in the ANN to predict a maintenance service of the vehicle. The memory units of the input partition can be configured for enhanced endurance, cyclic sequential overwrite of a continuous input stream.

Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.

Abstract: The present disclosure generally relates to optimizing device interrupt coalescing based upon host device behavior. The data storage device maintains three functional states: a training state, a holding state, and a retraining state. The data storage device switches between states based upon host device behavior as well as the behavior of the data storage device. Once the data storage device finds the optimum conditions for coalescing, the data storage device will periodically test the conditions to adapt to changing host device behavior as well as data storage device behavior. In so doing, the data storage device can dynamically adjust interrupt coalescing to ensure optimum operation of the storage device.

Abstract: The disclosed embodiments provide a system for processing scoring requests. During operation, the system matches an identifier for an entity in a scoring request to a cache entry in a score cache. Next, the system retrieves, from the cache entry, a previous value of a score generated by a machine learning model from previous values of features for the entity and a first encoded representation of the previous values of a subset of the features with greater than a threshold effect on the score. The system then compares the first encoded representation with a second encoded representation of the most recent values of the subset of the features for the entity. When the comparison indicates that the most recent values match the previous values, the system outputs the previous value of the score for the entity in a response to the scoring request.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

Abstract: Storage devices may be configured to desirably reduce the time required to perform a physical secure erase operation. The storage device includes a controller that is configured to direct the storage device to receive a physical secure erase command. The storage device can then identify the one or more blocks within the memory array for secure erasure based on the received physical secure erase command. For each block identified for erasure, the storage device further evaluates the block to determine the level type of cells within the block. In response to the cell level type being single-level, a single-cell erase command is issued to perform a single-level cell erase on the block. Conversely, in response to the cell level type being a higher-dimensional cell, a modified single-cell erase command to perform a modified single-level cell erase on the block is issued.

Abstract: A processing-in-memory (PIM) device includes a first group of storage regions, a second group of storage regions, and a plurality of multiplication/accumulation (MAC) operators. The MAC operators are configured to communicate with the first and second groups of storage regions through a global data input/output (GIO) line. A first storage region corresponding to a storage region of the first group of storage regions, a second storage region corresponding to a storage region of the second group of storage regions, and a first MAC operator corresponding to a MAC operator of the plurality of MAC operators constitute a MAC unit. The first MAC operator is configured to receive first data and second data from the first and second storage regions, respectively, through the GIO line to perform a MAC arithmetic operation of the first and second data and to output a result of the MAC arithmetic operation.